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11. 发明授权

US08466702B2 Test system and substrate unit for testing 有权
标题翻译：测试系统和基板单元进行测试
公开(公告)号：US08466702B2
公开(公告)日：2013-06-18
申请号：US12953352
申请日：2010-11-23
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： G01R31/20 , G01R31/02
CPC分类号： G01R31/2889
摘要： A test system that tests a plurality of chips under test formed on a wafer under test, the test system comprising a plurality of test substrates that are arranged in overlapping layers and that each have a plurality of test circuits, whose function is determined for each wafer, formed thereon; a plurality of connecting sections that electrically connect, to the chips under test, the test circuits formed on one of the test substrates; and a control apparatus that controls each of the test circuits. Each test substrate has test circuits, with a function predetermined for each substrate, formed thereon.
摘要翻译：一种在被测晶片上测试被测试的多个待测芯片的测试系统，所述测试系统包括多个测试基板，所述多个测试基板布置在重叠层中，并且每个具有多个测试电路，每个测试电路的功能是针对每个晶片，形成在其上多个连接部，其将与测试用芯片电连接的测试电路形成在一个测试基板上; 以及控制每个测试电路的控制装置。每个测试基板具有在其上形成的具有对于每个基板预定的功能的测试电路。

12. 发明授权

US08378700B2 Wafer unit for testing semiconductor chips and test system 有权
标题翻译：晶圆单元用于测试半导体芯片和测试系统
公开(公告)号：US08378700B2
公开(公告)日：2013-02-19
申请号：US12953362
申请日：2010-11-23
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： G01R31/20
CPC分类号： G01R31/2884 , G01R31/2831
摘要： Provided is a test wafer unit for testing a plurality of semiconductor chips formed on a semiconductor wafer, the test wafer unit including: a test wafer having a shape corresponding to a shape of the semiconductor wafer; and a plurality of test circuits formed on the test wafer, each test circuit provided to correspond to two or more of the plurality of semiconductor chips and testing the two or more semiconductor chips. The test wafer unit may include a plurality of connection terminals formed on the test wafer in one to one relation with test terminals of the plurality of semiconductor chips, where each of the plurality of connection terminals is connected to a corresponding one of the test terminals.
摘要翻译：提供了一种用于测试形成在半导体晶片上的多个半导体芯片的测试晶片单元，该测试晶片单元包括：具有对应于半导体晶片形状的形状的测试晶片; 以及形成在所述测试晶片上的多个测试电路，每个测试电路被提供以对应于所述多个半导体芯片中的两个或更多个并且测试所述两个或更多个半导体芯片。测试晶片单元可以包括与多个半导体芯片的测试端子成一一关系的在测试晶片上形成的多个连接端子，其中多个连接端子中的每一个连接到相应的一个测试端子。

13. 发明授权

US08375340B2 Apparatus for manufacturing substrate for testing, method for manufacturing substrate for testing and recording medium 有权
标题翻译：用于制造用于测试的基板的装置，用于测试和记录介质的基板的制造方法
公开(公告)号：US08375340B2
公开(公告)日：2013-02-12
申请号：US12952112
申请日：2010-11-22
申请人： Daisuke Watanabe , Masakatsu Suda , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Masakatsu Suda , Toshiyuki Okayasu
IPC分类号： G06F17/50
CPC分类号： G01R31/318511 , G01R31/31718
摘要： A test substrate manufacturing apparatus comprising a test circuit database that stores circuit data of a plurality of types of test circuits in association with a plurality of types of testing content; a definition information storing section that stores definition information defining arrangements of device pads of devices under test and testing content to be performed for each of the device pads; and a lithography data generating section that generates lithography data for the test substrate by (i) selecting, from the test circuit database, circuit data of each test circuit to be connected to a device pad based on the testing content defined by the definition information stored in the definition information storing section and (ii) determining positions on the test substrate where the test circuits corresponding to the selected circuit data are formed using lithography, based on the arrangements of the device pads as defined by the definition information.
摘要翻译：一种测试基板制造装置，包括：与多种测试内容相关联地存储多种类型的测试电路的电路数据的测试电路数据库; 定义信息存储部分，其存储定义要定义的装置的装置的定义信息，并且对每个装置焊盘执行测试内容; 以及光刻数据生成部，其通过以下步骤生成用于所述测试基板的光刻数据：（i）基于由所存储的所述定义信息定义的测试内容，从所述测试电路数据库中选择要连接到设备焊盘的每个测试电路的电路数据在定义信息存储部分中，以及（ii）基于由定义信息定义的装置焊盘的布置，确定测试基板上的位置，其中使用光刻形成与所选择的电路数据相对应的测试电路。

14. 发明申请

US20120319794A1 TEST APPARATUS FOR DIGITAL MODULATED SIGNAL 审中-公开
标题翻译：数字调制信号测试装置
公开(公告)号：US20120319794A1
公开(公告)日：2012-12-20
申请号：US13588823
申请日：2012-08-17
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： H03K7/00 , H03K9/00
CPC分类号： H04L27/34 , G01R31/31924 , H04L25/4917 , H04L27/362 , H04L27/38
摘要： A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers.
摘要翻译：测试装置包括以多个通道为增量提供的数字调制器。基带信号发生器使用可以调整定时信号的定时信号来执行数据输入的重新定时作为同相（正交）分量的调制信号，从而生成基带信号。驱动器产生具有与从基带信号发生器输出的基带信号对应的电平的多值数字信号。乘法器用多值数字信号对载波信号进行幅度调制。加法器对乘法器的输出信号求和。

15. 发明授权

US08270225B2 Data receiving circuit 失效
标题翻译：数据接收电路
公开(公告)号：US08270225B2
公开(公告)日：2012-09-18
申请号：US12532134
申请日：2008-03-18
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： G11C7/10
CPC分类号： G01R31/3191 , G01R31/31937
摘要： A variable delay circuit provides an adjustable delay to a strobe signal. An input latch circuit latches each bit data included in internal serial data by a strobe signal delayed by the variable delay circuit. A delay set unit adjusts a delay amount provided to the strobe signal by the variable delay circuit. While a calibration operation is being executed in which a known calibration pattern is inputted as serial data, the delay set unit statistically acquires output latch data of the input latch circuit, and adjusts the delay amount such that probabilities of occurrence of 1 and 0 becomes a predetermined ratio.
摘要翻译：可变延迟电路为选通信号提供可调延迟。输入锁存电路通过可变延迟电路延迟的选通信号来锁存内部串行数据中包含的每个位数据。延迟设定单元通过可变延迟电路来调整提供给选通信号的延迟量。当正在执行其中输入已知校准图案作为串行数据的校准操作时，延迟设置单元统计地获取输入锁存电路的输出锁存数据，并调整延迟量，使得出现1和0的概率变为预定比例。

16. 发明授权

US08269569B2 Test apparatus for digital modulated signal 有权
标题翻译：数字调制信号测试装置
公开(公告)号：US08269569B2
公开(公告)日：2012-09-18
申请号：US12918751
申请日：2009-02-20
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： H04L27/20
CPC分类号： H04L27/34 , G01R31/31924 , H04L25/4917 , H04L27/362 , H04L27/38
摘要： A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers.
摘要翻译：测试装置包括以多个通道为增量提供的数字调制器。基带信号发生器使用可以调整定时信号的定时信号来执行数据输入的重新定时作为同相（正交）分量的调制信号，从而生成基带信号。驱动器产生具有与从基带信号发生器输出的基带信号对应的电平的多值数字信号。乘法器用多值数字信号对载波信号进行幅度调制。加法器对乘法器的输出信号求和。

17. 发明申请

US20120215013A1 HYDROGEN STORAGE MATERIAL 有权
标题翻译：氢储存材料
公开(公告)号：US20120215013A1
公开(公告)日：2012-08-23
申请号：US13501538
申请日：2010-09-14
申请人： Ai Minoda , Shinji Oshima , Daisuke Watanabe
发明人： Ai Minoda , Shinji Oshima , Daisuke Watanabe
IPC分类号： C07D309/38 , C07C49/647 , C07C63/66 , C07C39/205
CPC分类号： C01B31/08 , B01J20/20 , B01J20/3204 , B01J20/3248 , B82Y30/00 , C01B3/0021 , C01B3/0026 , C01B32/342 , C01B32/354 , Y02E60/325 , Y02E60/327
摘要： The invention provides a hydrogen storage material comprising a porous carbon material having oxygen-containing functional groups on the surface, and Li bonded to the surface of the porous carbon material. The hydrogen storage material of the invention has more excellent hydrogen storage capacity than the prior art.
摘要翻译：本发明提供了一种储氢材料，其包括在表面具有含氧官能团的多孔碳材料，和结合到多孔碳材料表面的Li。本发明的储氢材料比现有技术具有更优异的储氢能力。

18. 发明申请

US20120158348A1 TIMING GENERATOR 失效
标题翻译：时序发生器
公开(公告)号：US20120158348A1
公开(公告)日：2012-06-21
申请号：US13409030
申请日：2012-02-29
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： G06F19/00
CPC分类号： G01R31/31725 , G01R31/3016
摘要： A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data.
摘要翻译：延迟设定数据发生器基于速率数据生成延迟设定数据。参考预定义的单位延迟量，可变延迟电路将测试图形数据延迟由延迟设置数据确定的延迟时间。第一速率数据以由单位延迟量确定的精度指定测试图案数据的周期。第二速率数据指定具有比单位延迟量确定的精度高的测试图案数据的周期。延迟设定数据发生器以由第二速率数据确定的比例以时分方式输出第一值和第二值，第一和第二值由第一速率数据确定。

19. 发明授权

US08191843B2 Mudguard mounting structure 有权
标题翻译：防水安装结构
公开(公告)号：US08191843B2
公开(公告)日：2012-06-05
申请号：US13016277
申请日：2011-01-28
申请人： Tatsuhiro Hagino , Daisuke Watanabe
发明人： Tatsuhiro Hagino , Daisuke Watanabe
IPC分类号： A47B96/00
CPC分类号： B60R11/00 , F16B2/02
摘要： There is provided a mudguard mounting structure, superior in versatility and capable of reducing the number of steps for mounting. The present invention is a structure for mounting a mudguard on a rear bumper of a vehicle, in which a mounting member is used to mount the mudguard on the rear bumper, said mounting member comprising a clamping portion on one side thereof for clamping an end portion of the rear bumper, and a mounting portion on which the mudguard is mounted on an other side. The mounting member can be mounted on the rear bumper by allowing the clamping portion to clamp the aforementioned end portion, thereby reducing the number of parts and steps for mounting, and costs. Since the mounting member excels in versatility, costs can be further reduced. An engagement portion for engaging the rear bumper is provided on an inner surface of the clamping portion.
摘要翻译：提供了一种隔板安装结构，其通用性优异，能够减少安装步数。本发明是一种用于将挡泥板安装在车辆的后保险杠上的结构，其中使用安装构件将挡泥板安装在后保险杠上，所述安装构件在其一侧包括夹紧部分，用于夹紧端部的后保险杠，以及安装部，挡泥板安装在另一侧。通过允许夹持部夹紧前述端部，可以将安装构件安装在后保险杠上，从而减少了安装的部件和步骤的数量以及成本。由于安装构件具有多功能性，因此可以进一步降低成本。用于接合后保险杠的接合部分设置在夹紧部分的内表面上。

20. 发明申请

US20110292532A1 STORAGE DEVICE AND METHOD FOR CONTROLLING PROJECTION AMOUNT OF HEAD 有权
标题翻译：用于控制头部投影量的存储装置和方法
公开(公告)号：US20110292532A1
公开(公告)日：2011-12-01
申请号：US13031024
申请日：2011-02-18
申请人： Daisuke Watanabe
发明人： Daisuke Watanabe
IPC分类号： G11B20/18
CPC分类号： G11B20/1879 , G11B5/607 , G11B20/10305 , G11B20/10388 , G11B20/10509 , G11B27/36 , G11B2220/2516
摘要： According to one embodiment, a storage device includes a recording medium, a driving module, a head, a conductive body, a write-verify module, and a projection amount controller. A conductive body is mounted on the head, and changes a projection amount of the head by thermally expanding the head with heat from a current carried by the conductive body. The write-verify module executes a write-verify check to check whether content written in any location on the recording medium is correct when the driving module starts rotating the recording medium. The projection amount controller controls the projection amount of the head by adding a first value to a current in a steady state carried by the conductive body if the content is correct, and adding a second value with an absolute value greater than that of the first value to the current in the steady state if the content is not correct.
摘要翻译：根据一个实施例，存储装置包括记录介质，驱动模块，头部，导电体，写入验证模块和投影量控制器。导电体安装在头部上，并且通过用导电体承载的电流的热量使头部热膨胀来改变头部的突出量。写入验证模块执行写入验证检查以在驱动模块开始旋转记录介质时，检查写入记录介质中任何位置的内容是否正确。投影量控制器如果内容正确，则通过将由导电体承载的稳定状态中的电流加上第一值来控制头的投影量，并且添加绝对值大于第一值的绝对值的第二值如果内容不正确，则处于稳定状态。

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