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11. 发明授权

US07759987B2 Multi-channel semiconductor integrated circuit 有权
标题翻译：多通道半导体集成电路
公开(公告)号：US07759987B2
公开(公告)日：2010-07-20
申请号：US12048895
申请日：2008-03-14
申请人： Naoki Hishikawa , Hiroki Matsunaga , Jinsaku Kaneda
发明人： Naoki Hishikawa , Hiroki Matsunaga , Jinsaku Kaneda
IPC分类号： H03B1/00
CPC分类号： H03K3/35613
摘要： A semiconductor integrated circuit includes a high-side transistor, a low-side transistor, a level shift circuit for driving the high-side transistor, and a pre-driver circuit for driving the low-side transistor. A connection point of the high-side transistor and the low-side transistor serves as an output terminal. The level shift circuit has first and second N-type MOS transistors whose gates are driven by the pre-driver circuit. The semiconductor integrated circuit further includes a diode whose anode is connected to the drain of the first or second N-type MOS transistor to which the gate of the high-side transistor is not connected, and whose cathode is connected to the output terminal.
摘要翻译：半导体集成电路包括高侧晶体管，低侧晶体管，用于驱动高侧晶体管的电平移位电路和用于驱动低侧晶体管的预驱动电路。高侧晶体管和低侧晶体管的连接点用作输出端子。电平移位电路具有第一和第二N型MOS晶体管，其栅极由预驱动器电路驱动。半导体集成电路还包括其阳极连接到第一或第二N型MOS晶体管的漏极的二极管，高侧晶体管的栅极未连接到该漏极，并且其阴极连接到输出端子。

12. 发明申请

US20090085899A1 CAPACITIVE LOAD DRIVING CIRCUIT AND PLASMA DISPLAY PANEL 审中-公开
标题翻译：电容负载驱动电路和等离子显示面板
公开(公告)号：US20090085899A1
公开(公告)日：2009-04-02
申请号：US12181595
申请日：2008-07-29
申请人： Hiroshi ANDO , Seiya Yoshida , Hiroki Matsunaga , Jinsaku Kaneda
发明人： Hiroshi ANDO , Seiya Yoshida , Hiroki Matsunaga , Jinsaku Kaneda
IPC分类号： G09G5/00 , G09G3/28
CPC分类号： G09G3/296 , G09G3/293 , G09G3/2948 , G09G2310/0218 , G09G2310/066 , G09G2330/028
摘要： A scan driving circuit includes: a shift register section receiving a scan data signal and a scan clock signal; a plurality of pulse width control circuits each receiving an output signal from the shift register section and a negative pulse width control signal to output a signal whose pulse width is controlled based on the negative pulse width control signal; a blanking section receiving the output signals from the plurality of pulse width control circuits and a blanking signal; and a plurality of high voltage output sections for amplifying the output signals from the plurality of pulse width control circuits, which are received via the blanking section, to successively output negative pulses each having a controlled pulse width to the scanning electrodes.
摘要翻译：扫描驱动电路包括：接收扫描数据信号和扫描时钟信号的移位寄存器部分; 多个脉冲宽度控制电路，各自接收来自移位寄存器部分的输出信号和负脉冲宽度控制信号，以输出基于负脉冲宽度控制信号来控制其脉冲宽度的信号; 接收来自多个脉冲宽度控制电路的输出信号的消隐部分和消隐信号; 以及多个高电压输出部分，用于放大经由消隐部分接收的多个脉冲宽度控制电路的输出信号，以连续向扫描电极输出每个具有受控脉冲宽度的负脉冲。

13. 发明授权

US07495296B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07495296B2
公开(公告)日：2009-02-24
申请号：US11139590
申请日：2005-05-31
申请人： Eisaku Maeda , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Masahiko Sasada
发明人： Eisaku Maeda , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Masahiko Sasada
IPC分类号： H01L29/94
CPC分类号： H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to increase a degree of integration in the semiconductor integrated circuit and stabilize output characteristics. A ternary circuit is formed by arranging a second high-side transistor, a diode, a second level shift circuit on one hand, and a low-side transistor, a first high-side transistor, a first level shift circuit, and a pre-driver on the other, so that each of cells are arranged in a row and an output bonding pad is placed between the second high-side transistor and the low-side transistor, wherein a cell width of the first level shift circuit, second level shift circuit and pre-driver corresponds to a cell width of the low-side transistor.
摘要翻译：本发明涉及多通道半导体集成电路的布局，并提供具有三元电路的半导体集成电路的布局，以增加半导体集成电路中的集成度并稳定输出特性。一方面通过布置第二高侧晶体管，二极管，第二电平移位电路和低端晶体管，第一高侧晶体管，第一电平移位电路和预置电路来形成三元电路，驱动器，使得每个单元排列成一行，并且输出接合焊盘放置在第二高侧晶体管和低侧晶体管之间，其中第一电平移位电路的单元宽度，第二电平移位电路和预驱动器对应于低侧晶体管的单元宽度。

14. 发明授权

US07365945B2 Magnetic head suspension with a lift tab 有权
标题翻译：带抬头的磁头悬挂
公开(公告)号：US07365945B2
公开(公告)日：2008-04-29
申请号：US11050447
申请日：2005-02-04
申请人： Yasuo Fujimoto , Satoru Takasugi , Hiroki Matsunaga
发明人： Yasuo Fujimoto , Satoru Takasugi , Hiroki Matsunaga
IPC分类号： G11B5/54
CPC分类号： G11B5/4826 , G11B5/4833
摘要： There is provided a magnetic head suspension including: a flexure portion which has a magnetic head mount area for supporting a magnetic head slider; a load bend portion which generates a load for pressing the magnetic head slider to a storage surface of a storage medium; a load beam portion which transmits the load to the magnetic head mount area; and a base portion which supports a base end region of the load bend portion. The load beam portion integrally includes a body in which at least a tip end portion thereof extends along a first plane approximately in parallel with the storage surface of the storage medium, and a lift tab extending forward from the tip end portion. The lift tab includes an engaging portion extending along a second plane which is approximately in parallel with the first plane and is positioned upper than the first plane so as to be spaced apart from the storage surface of the storage medium, and an inclined portion extending between the tip end portion of the body and the engaging portion. The load beam portion further includes a pair of flanges on both side edges in a width direction. The pair of side edges are positioned at least over the tip end portion and the inclined portion.
摘要翻译：提供了一种磁头悬架，包括：挠曲部分，其具有用于支撑磁头滑块的磁头安装区域; 负载弯曲部，其产生用于将磁头滑块按压到存储介质的存储表面的负载; 负载梁部，其将负载传递到磁头安装区域; 以及支撑负载弯曲部的基端部的基部。负载梁部分一体地包括主体，其中至少其末端部分沿着与存储介质的存储表面大致平行的第一平面延伸，以及从顶端部向前延伸的提升片。提升片包括沿着与第一平面大致平行的第二平面延伸并且定位在第一平面上方以与存储介质的存储表面间隔开的接合部分和在存储介质的存储表面之间延伸的倾斜部分主体的前端部和接合部。负载梁部分还包括在宽度方向上的两个侧边缘上的一对凸缘。一对侧边缘至少位于前端部分和倾斜部分之上。

15. 发明申请

US20070268059A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：US20070268059A1
公开(公告)日：2007-11-22
申请号：US11749266
申请日：2007-05-16
申请人： Tomohisa SAKAGUCHI , Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Eisaku Maeda
发明人： Tomohisa SAKAGUCHI , Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Eisaku Maeda
IPC分类号： H03L5/00
CPC分类号： H03K19/00315
摘要： A semiconductor integrated circuit device capable of securely preventing the output from becoming indefinite even when power is turned ON or OFF or even in a transient state in which the power voltage varies abruptly. In the semiconductor integrated circuit device, a protection circuit compares the power voltage from a first power supply terminal with a reference voltage, detects power ON, power OFF and abrupt power voltage variation, and outputs a reset command signal so that the output at the output terminal has a high impedance at the time of power ON, power OFF and abrupt power voltage variation.
摘要翻译：即使电源接通或断开，或即使在电源电压突然变化的过渡状态下，也能够可靠地防止输出变得不确定的半导体集成电路器件。在半导体集成电路装置中，保护电路将来自第一电源端子的电源电压与参考电压进行比较，检测电源接通，断电和突然的电源电压变化，并输出复位指令信号，使得输出端端子在电源接通，电源关闭和突然的电源电压变化时具有高阻抗。

16. 发明申请

US20060119389A1 Circuit for generating ternary signal 失效
标题翻译：用于产生三态信号的电路
公开(公告)号：US20060119389A1
公开(公告)日：2006-06-08
申请号：US11290062
申请日：2005-11-30
申请人： Jinsaku Kaneda , Akihiro Maejima , Hiroki Matsunaga , Eisaku Maeda , Hiroshi Ando
发明人： Jinsaku Kaneda , Akihiro Maejima , Hiroki Matsunaga , Eisaku Maeda , Hiroshi Ando
IPC分类号： H03K19/00
CPC分类号： H03K3/00 , H03K17/00 , H03K17/693
摘要： A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal. The circuit includes first to third transistors, each source terminal thereof is respectively connected to the three power supplies, and a sequential circuit that outputs control signals controlling the transistors. The sequential circuit outputs control signals that make the first and the third transistors be switched in a complementary manner in an initial state, and make the second and the third transistors be switched in a state that it is released from the initial state.
摘要翻译：用于产生接收二进制输入控制信号和二进制复位信号并输出三进制信号的三态信号的电路。电路包括第一至第三晶体管，其每个源极分别连接到三个电源，以及输出控制晶体管的控制信号的顺序电路。顺序电路输出使得第一和第三晶体管在初始状态下以互补方式切换的控制信号，并且使第二和第三晶体管在从初始状态释放的状态下被切换。

17. 发明授权

US07989964B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07989964B2
公开(公告)日：2011-08-02
申请号：US12094494
申请日：2006-09-29
申请人： Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando , Eisaku Maeda
发明人： Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando , Eisaku Maeda
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L27/12 , G09G3/296 , H01L24/06 , H01L24/49 , H01L27/0207 , H01L27/11898 , H01L2224/05554 , H01L2224/06179 , H01L2224/49179 , H01L2924/00014 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： On a semiconductor chip in a semiconductor integrated circuit, a plurality of circuit cells each of which has a pad are formed along a first chip side of the semiconductor chip. Among the plurality of circuit cells, one or more circuit cells at least in the vicinity of an end portion on the first chip side are arranged having a steplike shift in a direction apart from the first chip side with decreasing distance from the center portion to the end portion on the first chip side.
摘要翻译：在半导体集成电路中的半导体芯片上，沿着半导体芯片的第一芯片侧形成有具有焊盘的多个电路单元。在多个电路单元中，至少在第一芯片侧的端部附近的一个或多个电路单元被布置成沿着与第一芯片侧分开的方向具有阶梯状移位，其中心部分到中间部分的距离减小第一芯片侧的端部。

18. 发明授权

US07323923B2 Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：US07323923B2
公开(公告)日：2008-01-29
申请号：US11211638
申请日：2005-08-26
申请人： Eisaku Maeda , Hiroshi Ando , Jinsaku Kaneda , Akihiro Maejima , Hiroki Matsunaga
发明人： Eisaku Maeda , Hiroshi Ando , Jinsaku Kaneda , Akihiro Maejima , Hiroki Matsunaga
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , G09G3/296 , G09G2330/04 , H03K3/012 , H03K19/0013
摘要： A driver circuit is provided for preventing generation of a pass-through current in a CMOS output unit even if a power supply voltage VDD supplied from a low voltage power supply drops below a recommended operating power supply voltage. The driver circuit includes a level shift unit having PMOS transistors and NMOS transistors, and a CMOS output unit having a PMOS transistor and an NMOS transistor. The source, drain and gate of one PMOS transistor are respectively connected to a high voltage power supply, a first contact and a second contact. The source, drain and gate of a second PMOS transistor are respectively connected to a high voltage power supply, the second contact and the first contact. The source of one NMOS transistor is grounded, the drain thereof is connected to the first contact, and the gate thereof receives a low voltage signal. The source of a second NMOS transistor is grounded, the drain thereof is connected to the second contact, and the gate thereof receives a low voltage signal. In this driver circuit, the driving current of the one PMOS transistor is higher than the driving current of the one NMOS transistor.
摘要翻译：即使从低电压电源提供的电源电压VDD低于推荐的工作电源电压，也提供用于防止在CMOS输出单元中产生通过电流的驱动电路。驱动器电路包括具有PMOS晶体管和NMOS晶体管的电平移位单元和具有PMOS晶体管和NMOS晶体管的CMOS输出单元。一个PMOS晶体管的源极，漏极和栅极分别连接到高压电源，第一触点和第二触点。第二PMOS晶体管的源极，漏极和栅极分别连接到高压电源，第二触点和第一触点。一个NMOS晶体管的源极接地，其漏极连接到第一触点，其栅极接收低电压信号。第二NMOS晶体管的源极接地，其漏极连接到第二触点，并且其栅极接收低电压信号。在该驱动电路中，一个PMOS晶体管的驱动电流高于一个NMOS晶体管的驱动电流。

19. 发明申请

US20070273412A1 Drive voltage supply circuit 有权
标题翻译：驱动电源电路
公开(公告)号：US20070273412A1
公开(公告)日：2007-11-29
申请号：US11802635
申请日：2007-05-24
申请人： Seiya Yoshida , Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
发明人： Seiya Yoshida , Hiroki Matsunaga , Akihiro Maejima , Jinsaku Kaneda , Hiroshi Ando
IPC分类号： H03B1/00
CPC分类号： G09G3/296 , G09G3/293 , G09G2310/0275 , G09G2330/06
摘要： A drive voltage supply circuit has a first wire line, a second wire line, a first drive circuit, a plurality of second drive circuits, a control circuit for driving the first drive circuit and the plurality of second drive circuits, and an impedance element connected between the first wire line and each of output terminals.
摘要翻译：驱动电压供给电路具有第一有线线路，第二线路线路，第一驱动电路，多个第二驱动电路，用于驱动第一驱动电路和多个第二驱动电路的控制电路，以及连接有阻抗元件的阻抗元件在第一线路和每个输出端子之间。

20. 发明授权

US06906489B2 Stepping motor drive device and method 有权
标题翻译：步进电机驱动装置及方法
公开(公告)号：US06906489B2
公开(公告)日：2005-06-14
申请号：US10793342
申请日：2004-03-05
申请人： Shingo Fukamizu , Hiroki Matsunaga
发明人： Shingo Fukamizu , Hiroki Matsunaga
IPC分类号： H02P8/12 , H02P8/16 , H02P8/20 , H02P8/32
CPC分类号： H02P8/20 , H02P8/16
摘要： A reference signal generation unit generates a reference signal VCA showing a current limit value with a staircase waveform. A PWM control unit compares a measurement signal SENA obtained by a coil current measurement unit with the reference signal VCA at intervals of a PWM timing signal generated by a PWM timing signal generation unit, and switches transistors of a bridge rectification circuit ON and OFF according to the comparison, thereby PWM controlling a supply current to a coil. A discharge instruction signal generation unit issues a discharge instruction signal MMCPA when the reference signal VCA decreases. In response, a PWM control unit forms a current path in the bridge rectification circuit to cause a regenerative current to flow back into a power supply and capacitor.
摘要翻译：参考信号生成单元生成表示具有阶梯波形的电流限制值的基准信号VCA。 PWM控制单元将由线圈电流测量单元获得的测量信号SENA与由PWM定时信号生成单元生成的PWM定时信号的间隔与参考信号VCA进行比较，并且根据进行比较，从而PWM控制到线圈的电源电流。当参考信号VCA减小时，放电指令信号产生单元发出放电指令信号MMCPA。作为响应，PWM控制单元在桥式整流电路中形成电流路径，以使再生电流回流到电源和电容器中。

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