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11. 发明授权

US07821110B2 Circuit structures and methods with BEOL layer(s) configured to block electromagnetic interference 有权
标题翻译： BEOL层的电路结构和方法被配置为阻止电磁干扰
公开(公告)号：US07821110B2
公开(公告)日：2010-10-26
申请号：US11747342
申请日：2007-05-11
申请人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , Choongyeun Cho
发明人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , Choongyeun Cho
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL layer includes a conductive pattern defined at least partially by a plurality of elements arrayed in a first direction and a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in at least one of the first and second directions to block electromagnetic interference of a particular wavelength from passing therethrough. In one implementation, a first conductive pattern of a first BEOL layer polarizes electromagnetic interference, and a second conductive pattern of a second BEOL layer blocks the polarized electromagnetic interference.
摘要翻译：提供后端（BEOL）电路结构和方法来阻止外部来源或内部产生的电磁干扰。一种这样的BEOL电路结构包括支撑一个或多个集成电路的一个或多个半导体衬底以及设置在半导体衬底之上的一个或多个BEOL层。至少一个BEOL层包括至少部分地由在第一方向和第二方向排列的多个元件至少部分地限定的导电图案。多个元件的大小和位置在第一和第二方向中的至少一个方向上，以阻止特定波长的电磁干扰通过。在一个实施方案中，第一BEOL层的第一导电图案使电磁干扰偏振，并且第二BEOL层的第二导电图案阻挡极化的电磁干扰。

12. 发明授权

US07495519B2 System and method for monitoring reliability of a digital system 失效
标题翻译：监控数字系统可靠性的系统和方法
公开(公告)号：US07495519B2
公开(公告)日：2009-02-24
申请号：US11742018
申请日：2007-04-30
申请人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic , Hong Hua Song
发明人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic , Hong Hua Song
IPC分类号： G01R23/00 , H03B5/24 , H03K3/03
CPC分类号： G01R31/31937 , G01R31/31725
摘要： System and method are provided for continually monitoring reliability, or aging, of a digital system and for issuing a warning signal if digital system operation degrades past a specified threshold. The technique includes implementing a ring oscillator sensor in association with the digital system, wherein logic and/or device percent composition of the ring oscillator sensor mirrors percent composition thereof within the digital system. Counter logic is coupled to the ring oscillator sensor for converting outputted count signals to an oscillation frequency, and control logic is coupled to the counter logic for periodically evaluating oscillation frequency of the ring oscillator sensor and generating a warning signal indicative of reliability degradation if at least one of: (i) a measured or estimated oscillation frequency is below a warning threshold frequency; or (ii) a measured or estimated rate of change in a difference between measured oscillation frequencies exceeds an acceptable rate of change threshold.
摘要翻译：提供系统和方法用于连续监视数字系统的可靠性或老化，并且如果数字系统操作降低到指定的阈值以上，则发出警告信号。该技术包括实现与数字系统相关联的环形振荡器传感器，其中环形振荡器传感器的逻辑和/或设备百分比组成反映数字系统内的其组成的百分比。计数器逻辑耦合到环形振荡器传感器，用于将输出的计数信号转换为振荡频率，并且控制逻辑耦合到计数器逻辑，用于周期性评估环形振荡器传感器的振荡频率，并产生指示可靠性降级的警告信号，如果至少以下之一：（i）测量或估计的振荡频率低于警告阈值频率; 或者（ii）所测量的振荡频率之间的测量或估计的变化率超过可接受的变化率阈值。

13. 发明申请

US20090132082A1 STRIPED ON-CHIP INDUCTOR 有权
标题翻译：带状片上电感器
公开(公告)号：US20090132082A1
公开(公告)日：2009-05-21
申请号：US12362877
申请日：2009-01-30
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L29/00 , G06F19/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译：提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积的设计规则检查规则。对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

14. 发明申请

US20080079114A1 STRIPED ON-CHIP INDUCTOR 失效
标题翻译：带状片上电感器
公开(公告)号：US20080079114A1
公开(公告)日：2008-04-03
申请号：US11536896
申请日：2006-09-29
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L29/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译：提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积的设计规则检查规则。对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

15. 发明申请

US20120223411A1 STRIPED ON-CHIP INDUCTOR 有权
标题翻译：带状片上电感器
公开(公告)号：US20120223411A1
公开(公告)日：2012-09-06
申请号：US13469464
申请日：2012-05-11
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译：提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积的设计规则检查规则。对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

16. 发明授权

US08227891B2 Striped on-chip inductor 有权
标题翻译：条形片上电感
公开(公告)号：US08227891B2
公开(公告)日：2012-07-24
申请号：US12362877
申请日：2009-01-30
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L21/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译：提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积的设计规则检查规则。对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

17. 发明申请

US20090138737A1 APPARATUS, METHOD AND PROGRAM PRODUCT FOR ADAPTIVE REAL-TIME POWER AND PERFOMANCE OPTIMIZATION OF MULTI-CORE PROCESSORS 有权
标题翻译：用于自适应实时功率和多核处理器的性能优化的装置，方法和程序产品
公开(公告)号：US20090138737A1
公开(公告)日：2009-05-28
申请号：US11946522
申请日：2007-11-28
申请人： Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/32
摘要： An apparatus, method and program product for optimizing core performance and power in of a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized.
摘要翻译：一种用于优化多核处理器的核心性能和功耗的设备，方法和程序产品。该装置包括耦合到时钟源的多核处理器，其为一个或多个核心提供时钟频率，耦合到每个核心的独立电源，用于向每个核心提供电源电压，以及耦合到锁相环到每个核心，用于动态调整提供给每个核心的时钟频率。该装置还包括耦合到每个核心并被配置为收集针对每个核心测量的性能数据和功耗数据的控制器，并且使用PLL电路来调整提供给核心的电源电压，使得所述操作核心频率核心大于为核心预设的规格核心频率，从而优化核心性能和功耗。

18. 发明申请

US20090138748A1 APPARATUS AND METHOD FOR MICRO PERFORMANCE TUNING OF A CLOCKED DIGITAL SYSTEM 失效
标题翻译：一种时钟数字系统的微观性能调谐的装置和方法
公开(公告)号：US20090138748A1
公开(公告)日：2009-05-28
申请号：US11946466
申请日：2007-11-28
申请人： Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency.
摘要翻译：一种用于微调微处理器中的核心的有效时钟频率的装置和方法。该装置包括具有至少一个具有逻辑的核心的微处理器，其配置成在状态之间转换，耦合到微处理器的时钟信号，时钟信号具有基于最坏情况时钟频率和预定时钟周期的预定时钟频率。所述装置还包括耦合到所述芯的至少一个电压降传感器，所述传感器被配置为产生用于检测所述磁芯中的电压降的输出信号，并且确定在所述时钟周期内是否检测到所述输出信号，以及如果输出信号未检测到，传感器动态地调整提供给核心的时钟信号的时钟周期，以允许更多的时间完成状态转换，使得动态调整时钟周期有效地改变有效的核心时钟频率。

19. 发明授权

US07504705B2 Striped on-chip inductor 失效
标题翻译：条形片上电感
公开(公告)号：US07504705B2
公开(公告)日：2009-03-17
申请号：US11536896
申请日：2006-09-29
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： G06F17/50
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译：提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积的设计规则检查规则。对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

20. 发明授权

US08937355B2 Striped on-chip inductor 有权
公开(公告)号：US08937355B2
公开(公告)日：2015-01-20
申请号：US13469464
申请日：2012-05-11
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L21/00 , H01L49/02 , H01L23/522 , H01L27/02 , H01F17/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

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