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11. 发明申请

US20120042228A1 BITWISE RELIABILITY INDICATORS FROM SURVIVOR BITS IN VITERBI DECODERS 有权
标题翻译： VITERBI解码器中的生存位置的可比性可靠性指标
公开(公告)号：US20120042228A1
公开(公告)日：2012-02-16
申请号：US12856143
申请日：2010-08-13
申请人： Andries Pieter Hekstra , Nur Engin
发明人： Andries Pieter Hekstra , Nur Engin
IPC分类号： H03M13/07 , G06F11/10 , G06F11/07
CPC分类号： H04L1/0054 , H03M13/09 , H03M13/2936 , H03M13/373 , H03M13/4138 , H03M13/4161 , H04L1/0059 , H04L1/0065
摘要： Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.
摘要翻译：各种实施例涉及擦除标志的产生，以指示由卷积码的解码产生的错误。维特比解码器可以使用寄存器交换方法来产生多个幸存代码。在定义的索引中，可以进行多数投票来比较每个幸存者代码中的比特值。这个多数投票可以涉及获得高阶位数量和低位数量，并获得两个数量的差。可以将高阶位与低位的差的绝对值与定义的阈值进行比较。当绝对值差低于定义的数量时，可以产生擦除标志并与定义的索引的位相关联，表示它们符合擦除条件。在一些实施例中，Reed-Solomon解码器可以使用擦除标志来针对特定的幸存者比特或幸存者字节来进行错误校正。

12. 发明申请

US20110087949A1 RECONFIGURABLE TURBO INTERLEAVERS FOR MULTIPLE STANDARDS 审中-公开
标题翻译：可重新启用的多种标准的TURBO INTERLEAVERS
公开(公告)号：US20110087949A1
公开(公告)日：2011-04-14
申请号：US12996783
申请日：2009-06-06
申请人： Angelo Raffaele Dilonardo , Nur Engin
发明人： Angelo Raffaele Dilonardo , Nur Engin
IPC分类号： H03M13/45 , H03M13/27 , G06F11/10
CPC分类号： H03M13/2775 , H03M13/2739 , H03M13/2753 , H03M13/2764 , H03M13/2957 , H03M13/6519 , H03M13/6525 , H03M13/6544
摘要： A data processing system, a turbo decoding system, an address generator and a method of reconfiguring a turbo decoding method is provided. The data processing system (101) comprises the turbo decoding system (100). The turbo decoding system (100) comprises electronic circuits. The electronic circuits comprises: a memory (108), the address generator (102), and a Soft Input Soft Output decoder (106). The address generator (102) is operative to produce a sequence of addresses according to an interleaving scheme. The address generator can support multiple interleaving schemes. The address generator (102) is operative to receive reconfiguration information. The address generator (102) is operative to reconfigure during operational use the interleaving scheme in dependency on the reconfiguration information.
摘要翻译：提供了一种数据处理系统，turbo解码系统，地址生成器和重新配置turbo解码方法。数据处理系统（101）包括turbo解码系统（100）。 turbo解码系统（100）包括电子电路。电子电路包括：存储器（108），地址生成器（102）和软输入软输出解码器（106）。地址发生器（102）可操作以根据交织方案产生地址序列。地址生成器可以支持多种交织方案。地址发生器（102）可操作以接收重配置信息。地址发生器（102）可操作以在操作期间根据重新配置信息重新配置交织方案。

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