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11. 发明授权

US08417874B2 High speed memory having a programmable read preamble 有权
标题翻译：具有可编程读取前置码的高速存储器
公开(公告)号：US08417874B2
公开(公告)日：2013-04-09
申请号：US12691633
申请日：2010-01-21
申请人： Clifford Alan Zitlaw , Anthony Le
发明人： Clifford Alan Zitlaw , Anthony Le
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C7/1072 , G11C7/20
摘要： The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.
摘要翻译：主题系统和/或方法涉及能够在制造之后更新前导码模式的高速存储器设备。高速存储器件可以包括闪存模块和RAM模块。 FLASH模块可以包括初始前导码模式，其中在高速存储器的加电期间加载初始前导码模式。 RAM模块可以包括默认前导码模式，其中在高速存储器上电之后加载默认前导码模式。可以通过制造高速存储器或高速存储器的OEM来定义初始前导码模式或默认前导码模式。另外，可以使用基于目标环境的定制前导码模式来更新初始前导码模式或默认前导码模式。

12. 发明申请

US20130060980A1 VARIABLE READ LATENCY ON A SERIAL MEMORY BUS 有权
标题翻译：串行存储器总线上的可变读取延迟
公开(公告)号：US20130060980A1
公开(公告)日：2013-03-07
申请号：US13668935
申请日：2012-11-05
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
IPC分类号： G06F13/14
CPC分类号： G06F13/161 , G06F13/1689 , G06F13/4291 , G11C7/22
摘要： Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.
摘要翻译：提供了有助于在串行存储器总线上采用可变读延迟的系统和/或方法。在一方面，存储器可以利用未定义的时间量从存储器阵列获取数据并准备用于在串行存储器总线上传送的数据。串行存储器总线可以被驱动到一个定义的状态。当数据准备好传输时，内存可以在串行存储器总线上断言启动位，以在启动数据传输之前通知主机。

13. 发明授权

US08244964B2 Read preamble for data capture optimization 有权
标题翻译：读取前导码用于数据捕获优化
公开(公告)号：US08244964B2
公开(公告)日：2012-08-14
申请号：US12646279
申请日：2009-12-23
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
IPC分类号： G06F12/00 , H04L12/56
CPC分类号： G11C16/32 , G11C16/26 , G11C2216/30
摘要： Systems and/or methods are provided that facilitate data capture optimization for devices accessing memories via a bus. In an aspect, a memory can output a read preamble prior to pushing data onto a bus. The read preamble can be a known sequence of one or more bits. A host device accessing the memory via the bus can analyze the read preamble and, particularly, timing characteristics of the read preamble. The timing characteristics can be utilized to identify an optimal capture point within a window of data validity.
摘要翻译：提供了用于经由总线访问存储器的设备的数据捕获优化的系统和/或方法。在一方面，存储器可以在将数据推送到总线之前输出读取前同步码。读取的前同步码可以是一个或多个比特的已知序列。通过总线访问存储器的主机设备可以分析读取前置码，特别是读取前置码的定时特性。时序特征可用于识别数据有效性窗口内的最佳捕获点。

14. 发明授权

US08966151B2 Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal 有权
标题翻译：包括读数据选通信号的减少引脚数（RPC）存储器总线接口的装置和方法
公开(公告)号：US08966151B2
公开(公告)日：2015-02-24
申请号：US13435445
申请日：2012-03-30
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
IPC分类号： G06F1/08 , G06F1/10
CPC分类号： G06F1/10 , G06F1/08 , G06F1/22
摘要： A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select for delivering a chip select signal that indicates when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device. The interface also includes a differential clock pair for delivering a differential clock signal. A read data strobe is included in the interface for delivering a read data strobe signal from the peripheral device. The interface includes a data bus for delivering command, address, and data information. The read data strobe indicates when valid data is present on the data bus.
摘要翻译：一种用于存储总线接口的方法和装置，包括读数据选通。该接口包括用于传递芯片选择信号的芯片选择，该芯片选择信号指示外围设备何时被激活，其中所述总线接口提供主机设备和所述外围设备之间的通信。该接口还包括用于传送差分时钟信号的差分时钟对。用于从外围设备传送读取数据选通信号的接口中包括读取数据选通脉冲。该接口包括用于传递命令，地址和数据信息的数据总线。读数据选通指示当数据总线上存在有效数据时。

15. 发明授权

US08806071B2 Continuous read burst support at high clock rates 有权
标题翻译：以高时钟速率连续读取突发支持
公开(公告)号：US08806071B2
公开(公告)日：2014-08-12
申请号：US13357842
申请日：2012-01-25
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
IPC分类号： G06F9/44 , G06F13/38
CPC分类号： G06F9/44 , G06F13/38 , G06F13/4243 , G11C7/222 , G11C2207/2272
摘要： A memory device includes a memory array, an output buffer, an initial latency register, and an output signal. Often times a host device that interfaces with the memory device is clocked at high rate such that data extraction rates of the memory device are not adequate to support a gapless data transfer. The output signal is operable to stall a transmission between the memory device and the host device when data extraction rates from the memory array are not adequate to support output rates of the output buffer.
摘要翻译：存储器件包括存储器阵列，输出缓冲器，初始延迟寄存器和输出信号。通常，与存储器件连接的主机设备以高速率被计时，使得存储器件的数据提取速率不足以支持无间隙数据传输。当来自存储器阵列的数据提取速率不足以支持输出缓冲器的输出速率时，输出信号可操作以阻止存储器件和主机器件之间的传输。

16. 发明授权

US08725920B2 Variable read latency on a serial memory bus 有权
标题翻译：串行存储器总线上的可变读延迟
公开(公告)号：US08725920B2
公开(公告)日：2014-05-13
申请号：US13668935
申请日：2012-11-05
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
IPC分类号： G06F13/42 , G06F13/00 , G06F3/00
CPC分类号： G06F13/161 , G06F13/1689 , G06F13/4291 , G11C7/22
摘要： Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.
摘要翻译：提供了有助于在串行存储器总线上采用可变读延迟的系统和/或方法。在一方面，存储器可以利用未定义的时间量从存储器阵列获取数据并准备用于在串行存储器总线上传送的数据。串行存储器总线可以被驱动到一个定义的状态。当数据准备好传输时，内存可以在串行存储器总线上断言启动位，以在启动数据传输之前通知主机。

17. 发明授权

US08327052B2 Variable read latency on a serial memory bus 有权
标题翻译：串行存储器总线上的可变读延迟
公开(公告)号：US08327052B2
公开(公告)日：2012-12-04
申请号：US12646291
申请日：2009-12-23
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
IPC分类号： G06F13/42 , G06F13/00 , G06F3/00
CPC分类号： G06F13/161 , G06F13/1689 , G06F13/4291 , G11C7/22
摘要： Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.
摘要翻译：提供了有助于在串行存储器总线上采用可变读延迟的系统和/或方法。在一方面，存储器可以利用未定义的时间量从存储器阵列获取数据并准备用于在串行存储器总线上传送的数据。串行存储器总线可以被驱动到一个定义的状态。当数据准备好传输时，内存可以在串行存储器总线上断言启动位，以在启动数据传输之前通知主机。

18. 发明申请

US20120066464A1 APPARATUS AND METHOD FOR PROGRAMMABLE READ PREAMBLE 有权
标题翻译：可编程读取前缀的装置和方法
公开(公告)号：US20120066464A1
公开(公告)日：2012-03-15
申请号：US12879936
申请日：2010-09-10
申请人： Clifford Alan Zitlaw , Anthony Le
发明人： Clifford Alan Zitlaw , Anthony Le
IPC分类号： G06F12/00 , G06F12/16
CPC分类号： G06F12/16 , G06F1/12 , G06F11/10 , G08B5/222 , G11C5/066 , G11C7/1006 , G11C7/222 , G11C11/5621 , G11C16/00 , H04L7/04
摘要： A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data.
摘要翻译：提供存储器件。该存储器件包括前置码存储器和存储器控制器。前导码存储器被布置为存储读取前导码，使得读取前导码包括适合于对准用于读取数据的捕获点的训练模式。此外，训练模式是可编程的，使得训练模式可以在制造前同步码存储器之后至少改变一次。响应于读取命令，存储器控制器提供存储在前导码存储器中的读取前导码以及读取的数据。

19. 发明申请

US20110238866A1 VARIABLE READ LATENCY ON A SERIAL MEMORY BUS 有权
标题翻译：串行存储器总线上的可变读取延迟
公开(公告)号：US20110238866A1
公开(公告)日：2011-09-29
申请号：US12729905
申请日：2010-03-23
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
IPC分类号： G06F13/38 , G06F12/00 , G06F3/00
CPC分类号： G06F13/161 , G06F13/4291
摘要： One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus.
摘要翻译：一个或多个实施例提供了通过串行输入/输出存储器数据接口从可变延迟存储器读取数据的方法和系统。该系统包括具有可变延迟访问时间的存储器，存储器控制器和将存储器控制器耦合到存储器的串行数据总线。存储器控制器将Read命令传送到存储器，并在有限的时间内迫使串行数据总线为低电平。然后存储器强制总线为低电平，然后存储器控制器释放总线。当存储器准备好提供数据时，存储器在串行数据总线上提供高信号。

20. 发明申请

US20110153900A1 VARIABLE READ LATENCY ON A SERIAL MEMORY BUS 有权
标题翻译：串行存储器总线上的可变读取延迟
公开(公告)号：US20110153900A1
公开(公告)日：2011-06-23
申请号：US12646291
申请日：2009-12-23
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
IPC分类号： G06F13/20
CPC分类号： G06F13/161 , G06F13/1689 , G06F13/4291 , G11C7/22
摘要： Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.
摘要翻译：提供了有助于在串行存储器总线上采用可变读延迟的系统和/或方法。在一方面，存储器可以利用未定义的时间量从存储器阵列获取数据并准备用于在串行存储器总线上传送的数据。串行存储器总线可以被驱动到一个定义的状态。当数据准备好传输时，内存可以在串行存储器总线上断言启动位，以在启动数据传输之前通知主机。

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