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11. 发明授权

US06271059B1 Chip interconnection structure using stub terminals 有权
标题翻译：使用短截线端子的芯片互连结构
公开(公告)号：US06271059B1
公开(公告)日：2001-08-07
申请号：US09225148
申请日：1999-01-04
申请人： Claude L. Bertin , William R. Tonti , Richard Q. Williams
发明人： Claude L. Bertin , William R. Tonti , Richard Q. Williams
IPC分类号： H01L2144
CPC分类号： H01L23/13 , H01L24/05 , H01L24/81 , H01L2224/0401 , H01L2224/81136 , H01L2224/81141 , H01L2224/81192 , H01L2224/81365 , H01L2224/81801 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/19041
摘要： A method for fabricating a connector structure for interconnecting integrated circuit chips. The method includes the steps of patterning, masking and etching a substrate to form protrusions on the top and/or bottom surfaces of the substrate. Then the protrusions are preferentially etched to form truncated protrusions. An integrated circuit chip having pads on its surface is then joined to the top and/or bottom sides of the substrate. The protrusions and pads are coated with an electrically conductive metal. The substrate and the integrated circuit chips are joined and aligned together such that the truncated protrusions mate with the pads. Metal-coated vias are formed through the substrate to electrically connect the integrated circuit chips on the surfaces of the substrate.
摘要翻译：一种用于制造用于互连集成电路芯片的连接器结构的方法。该方法包括对衬底进行图案化，掩模和蚀刻以在衬底的顶表面和/或底表面上形成凸起的步骤。然后优先蚀刻突起以形成截短的突起。然后，在其表面上具有焊盘的集成电路芯片接合到衬底的顶部和/或底部。突起和垫被涂覆有导电金属。基板和集成电路芯片被接合并对齐在一起，使得截短的突起与焊盘配合。通过衬底形成金属涂覆的通孔，以电连接衬底表面上的集成电路芯片。

12. 发明授权

US06222395B1 Single-ended semiconductor receiver with built in threshold voltage difference 失效
标题翻译：单端半导体接收器内置阈值电压差
公开(公告)号：US06222395B1
公开(公告)日：2001-04-24
申请号：US09225112
申请日：1999-01-04
申请人： Claude L. Bertin , Russell J. Houghton , William R. Tonti
发明人： Claude L. Bertin , Russell J. Houghton , William R. Tonti
IPC分类号： G05F110
CPC分类号： G05F3/205
摘要： A differential receiver for sensing small input voltage swings by using a built in reference voltage obtained by a difference in threshold voltage between a differential pair of closely spaced transistors. The difference in threshold voltage can be produced by different values of ion implantation of the gates of the transistor pair with the same material, or by dosages using different materials. The difference in threshold voltage can also be obtained by using different transistor channel lengths. The threshold voltages can also be modulated by the control of the transistor substrate voltages using a voltage control substrate means.
摘要翻译：一种差分接收器，用于通过使用通过差分对间隔晶体管之间的阈值电压差而获得的内置参考电压来感测小输入电压摆幅。阈值电压的差异可以通过使用相同材料的晶体管对的栅极的离子注入的不同值，或通过使用不同材料的剂量来产生。也可以通过使用不同的晶体管沟道长度来获得阈值电压的差异。也可以通过使用电压控制衬底装置控制晶体管衬底电压来调制阈值电压。

13. 发明授权

US06177809B1 Redundant input/output driver circuit 失效
标题翻译：冗余输入/输出驱动电路
公开(公告)号：US06177809B1
公开(公告)日：2001-01-23
申请号：US09322470
申请日：1999-05-28
申请人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
发明人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
IPC分类号： H03K19094
CPC分类号： H03K19/00384 , H03K19/0005
摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.
摘要翻译：由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态状态的第一个片外驱动电路。

14. 发明授权

US06177729B1 Rolling ball connector 失效
标题翻译：滚球连接器
公开(公告)号：US06177729B1
公开(公告)日：2001-01-23
申请号：US09303290
申请日：1999-04-03
申请人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
发明人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
IPC分类号： H01L2348
CPC分类号： H01L24/16 , G01R1/0483 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/83 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/11003 , H01L2224/11334 , H01L2224/13099 , H01L2224/13111 , H01L2224/1319 , H01L2224/17051 , H01L2224/2919 , H01L2224/8319 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H05K1/111 , H05K3/321 , H05K2201/0133 , H05K2201/0212 , H05K2201/0221 , H05K2201/0233 , H05K2201/10234 , H05K2201/10734 , H05K2201/10992 , H05K2203/0307 , Y10T428/12472 , H01L2924/00 , H01L2924/3512 , H01L2924/00014
摘要： An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.
摘要翻译：集成电路组件具有与滚动金属球电连接到衬底的焊盘的芯片焊盘。柔韧的材料将球与芯片和衬底的焊盘可动地接触。由于球相对自由移动，因此在现有技术的连接接头中通常会引起巨大应力的热膨胀差异简单地导致本发明的滚珠滚动，从而完全避免热应力。与C4焊料凸块相比，连接的可靠性大大提高，尽管存在大量的热失配，芯片可以安全地直接安装到诸如PC板的基板上。

15. 发明授权

US6111425A Very low power logic circuit family with enhanced noise immunity 有权
标题翻译：超低功耗逻辑电路系列，具有增强的抗噪声能力
公开(公告)号：US6111425A
公开(公告)日：2000-08-29
申请号：US173436
申请日：1998-10-15
申请人： Claude L. Bertin , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K19/003 , H03K3/356 , H03K19/173 , H03K17/16
CPC分类号： H03K3/356113 , H03K19/1738
摘要： A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.
摘要翻译：一个非常低功率的逻辑电路系列，有利地提供1）保持高性能，2）显着降低的功耗，和3）增强的抗噪声能力。在第一组实施例中，使用双轨互补逻辑信号来提高对外部噪声的电路抗扰性并且减少由逻辑电路本身产生的噪声。本发明的接收机部分包括具有两个门到两个源的交叉耦合的两个输入FET。在一个优选实施例中，接收器和驱动器部分都连接在具有所有N个通道驱动器的中继器中。第二组实施例在不平衡接收机中具有单侧输入，包括到栅极N沟道的交叉耦合源极和栅极P沟道输出晶体管的交叉耦合漏极。

16. 发明授权

US06437385B1 Integrated circuit capacitor 失效
标题翻译：集成电路电容
公开(公告)号：US06437385B1
公开(公告)日：2002-08-20
申请号：US09607094
申请日：2000-06-29
申请人： Claude L. Bertin , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10832 , H01L28/55 , H01L28/87 , H01L29/66181 , H01L29/945
摘要： Use of different materials for different conductive films forming plates or electrodes of one or more capacitors formed in a trench in a body of semiconductor materials allow connections to be made selectively to the plates. The films may be undercut by different etchants at respective connection apertures to avoid formation of connections or connections made by doped polysilicon of different conductivities forming connections to some plates of similarly doped polysilicon and blocking diode junctions with oppositely doped polysilicon. The blocking diodes may include a compensation implant to adjust reverse breakdown characteristics and provide transient and electrostatic discharge protection.
摘要翻译：对于形成在半导体材料体中的沟槽中的一个或多个电容器形成板或不同导电膜的不同材料的使用允许选择性地连接板。这些膜可能在相应的连接孔处被不同的蚀刻剂削弱，以避免由不同导电性的掺杂多晶硅形成的连接或连接形成连接到具有相反掺杂多晶硅的类似掺杂多晶硅和阻塞二极管结的某些平板。阻塞二极管可以包括补偿注入以调整反向击穿特性并提供瞬态和静电放电保护。

17. 发明授权

US06369671B1 Voltage controlled transmission line with real-time adaptive control 有权
标题翻译：电压控制传输线具有实时自适应控制
公开(公告)号：US06369671B1
公开(公告)日：2002-04-09
申请号：US09281412
申请日：1999-03-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01P1185
CPC分类号： G11C7/12
摘要： A semiconductor structure having a substrate, an insulator above a portion of the substrate, a conductor above the insulator; and at least two contact regions in the substrate on opposite sides of the portion of the substrate, wherein a voltage between the contact regions modulates a capacitance of the conductor.
摘要翻译：一种具有衬底的半导体结构，在衬底的一部分上方的绝缘体，绝缘体上方的导体; 以及在所述衬底的所述部分的相对侧上的所述衬底中的至少两个接触区域，其中所述接触区域之间的电压调制所述导体的电容。

18. 发明授权

US06346846B1 Methods and apparatus for blowing and sensing antifuses 失效
标题翻译：用于吹制和检测反熔丝的方法和装置
公开(公告)号：US06346846B1
公开(公告)日：2002-02-12
申请号：US09466479
申请日：1999-12-17
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
IPC分类号： H01H3776
CPC分类号： G11C5/145 , G11C17/18
摘要： Methods and apparatus for blowing and sensing antifuses are provided. Specifically, in a first aspect, a method is provided for changing the state of one of a plurality of antifuses by selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse. In second and third aspects, apparatus are provided for performing the method of the first aspect. In a fourth aspect, a method is provided for boosting a voltage that includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling about twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating about thrice the first voltage based on the second voltage of the second stage voltage booster circuit. In a fifth aspect, apparatus are provided for performing the method of the fourth aspect.
摘要翻译：提供了用于吹制和检测反熔丝的方法和装置。具体地，在第一方面中，提供一种通过选择一组反熔丝中的一个并且施加高电压来改变所选择的反熔丝的状态来改变多个反熔丝之一的状态的方法。在第二和第三方面中，提供了用于执行第一方面的方法的装置。在第四方面，提供了一种用于升压电压的方法，包括以下步骤：在第一级升压电路的第一级存储机构内产生第一电压，产生等于第一级升压电路中第一电压的大约两倍的第二电压，第二级升压电路的第二级第二级存储机构，并且基于第二级升压电路的第二电压产生约三倍的第一电压。在第五方面中，提供了用于执行第四方面的方法的装置。

19. 发明授权

US06195027B1 Capacitive precharging and discharging network for converting N bit input into M bit output 失效
标题翻译：用于将N位输入转换为M位输出的电容式预充放电网络
公开(公告)号：US06195027B1
公开(公告)日：2001-02-27
申请号：US09302744
申请日：1999-04-30
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , Steven W. Tomashot , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , Steven W. Tomashot , William R. Tonti
IPC分类号： H03M720
CPC分类号： G11C8/10
摘要： A method and structure for decoding n input signals and their complements to one of m output signals is provided. A capacitive network is provided having m output nodes. The output nodes are precharged to a given voltage value. N input signals and their complements are provided each having either a high value or a low value. At least one but less than all of the output nodes are discharged to a value less than the given voltage but greater than ground in output patterns responsive to given input patterns of the true and complement values of the input signals. The output patterns of the discharged nodes is such as to provide one and only one discharged or one and only one undischarged node for any given pattern of input signals. Preferably the capacitive network includes NMOS inversion capacitors.
摘要翻译：提供了用于将n个输入信号及其与m个输出信号之一的补码进行解码的方法和结构。提供具有m个输出节点的电容网络。输出节点预充电到给定的电压值。提供N个输入信号及其补码，每个具有高值或低值。响应于输入信号的真值和补码值的给定输入模式，至少一个但不到所有输出节点的输出模式被放电到小于给定电压但大于输出模式的输出值的值。放电节点的输出模式是为任何给定模式的输入信号提供一个且仅一个放电或一个且仅一个未充电节点。优选地，电容网络包括NMOS反转电容器。

20. 发明授权

US5761114A Multi-level storage gain cell with stepline 失效
标题翻译：带梯级的多级存储增益单元
公开(公告)号：US5761114A
公开(公告)日：1998-06-02
申请号：US803034
申请日：1997-02-19
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
IPC分类号： G11C11/56
CPC分类号： G11C11/565 , G11C16/30
摘要： A method and apparatus for using multi-level signals in a gain cell is shown. The method involves of first, storing a value of a multi-level signal in the gain cell. A stepping waveform is then applied to the gain cell and the gain cell outputs a conduction signal when the level of the stepping waveform corresponds to the value of the multilevel signal that is stored within the gain cell. Finally, the value of the multi-level signal is determined through the conduction signal and the corresponding level of the stepping waveform. The gain cell includes an input device, a storage device and a level comparator, which responds to the stepping waveform generated from a stepping signal generator and outputs the conduction signal for determining the value of the multi-level signal stored in the storage device.
摘要翻译：示出了在增益单元中使用多电平信号的方法和装置。该方法首先在增益单元中存储多电平信号的值。然后，当增益单元的步进波形对应于存储在增益单元内的多电平信号的值时，增益单元输出导通信号。最后，通过导通信号和步进波形的相应电平来确定多电平信号的值。增益单元包括响应于从步进信号发生器产生的步进波形的输入装置，存储装置和电平比较器，并输出用于确定存储在存储装置中的多电平信号的值的导通信号。

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