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11. 发明授权

US08225188B2 Apparatus for blind checksum and correction for network transmissions 有权
标题翻译：用于网络传输的盲校验和校正装置
公开(公告)号：US08225188B2
公开(公告)日：2012-07-17
申请号：US12200985
申请日：2008-08-29
申请人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
发明人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
IPC分类号： H03M13/00
CPC分类号： H04L69/16 , H04L1/0041 , H04L1/0061 , H04L1/0072 , H04L69/161
摘要： Apparatus for providing a checksum in a network transmission. In one aspect of the invention, a checksum for a packet to be transmitted on a network is determined by retrieving packet information from a storage device, the packet information to be included in the packet to be transmitted. A blind checksum value is determined based on the retrieved packet information, and the blind checksum value is adjusted to a protocol checksum based on descriptor information describing the structure of the packet. The protocol checksum is inserted in the packet before the packet is transmitted.
摘要翻译：用于在网络传输中提供校验和的装置。在本发明的一个方面，通过从存储设备检索分组信息来确定要在网络上发送的分组的校验和，所述分组信息将包括在要发送的分组中。基于检索的分组信息确定盲校验和值，并且基于描述分组的结构的描述符信息将盲校验和值调整为协议校验和。在分组发送之前，协议校验和被插入到分组中。

12. 发明授权

US07706409B2 System and method for parsing, filtering, and computing the checksum in a host Ethernet adapter (HEA) 有权
标题翻译：在主机以太网适配器（HEA）中解析，过滤和计算校验和的系统和方法
公开(公告)号：US07706409B2
公开(公告)日：2010-04-27
申请号：US11096365
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04J3/24
CPC分类号： H04L1/0052 , H04L1/0061
摘要： A system and method for parsing, filtering, and computing the checksum in a host Ethernet adapter (HEA) that is coupled to a host. The method includes receiving a part of a frame, wherein a plurality of parts of a frame constitute a entire frame. Next, parse the part of a frame before receiving the entire frame. The HEA computes a checksum of the part of a frame. The HEA filters the part of a frame based on a logical, port-specific policy and transmits the checksum to the host.
摘要翻译：用于在耦合到主机的主机以太网适配器（HEA）中解析，过滤和计算校验和的系统和方法。该方法包括接收帧的一部分，其中帧的多个部分构成整个帧。接下来，在接收整个帧之前解析帧的一部分。 HEA计算帧的一部分的校验和。 HEA基于逻辑，端口特定策略过滤帧的一部分，并将校验和传送到主机。

13. 发明授权

US07606166B2 System and method for computing a blind checksum in a host ethernet adapter (HEA) 失效
标题翻译：用于计算主机以太网适配器（HEA）中的盲校验和的系统和方法
公开(公告)号：US07606166B2
公开(公告)日：2009-10-20
申请号：US11097430
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
IPC分类号： H04L12/66
CPC分类号： H04L69/16 , H04L69/161
摘要： A system and method for computing a blind checksum includes a host Ethernet adapter (HEA) with a system for receiving a packet. The system determines whether or not the packet is in Internet protocol version four (IPv4). If the packet is not in IPv4, the system computes the checksum of the packet. If the packet is in IPv4, the system determines whether the packet is in transmission control protocol (TCP) or user datagram protocol (UDP). If the packet is not in either of TCP or UDP the system attaches a pseudo-header to the packet and computes the checksum of the packet based on the pseudo-header and the IPv4 standard.
摘要翻译：用于计算盲校验和的系统和方法包括具有用于接收分组的系统的主机以太网适配器（HEA）。系统确定数据包是否处于Internet协议版本四（IPv4）中。如果分组不在IPv4中，则系统计算分组的校验和。如果分组在IPv4中，则系统确定分组是否在传输控制协议（TCP）或用户数据报协议（UDP）中。如果分组不在TCP或UDP中，则系统将伪报头附加到分组，并基于伪报头和IPv4标准计算分组的校验和。

14. 发明授权

US07586936B2 Host Ethernet adapter for networking offload in server environment 失效
标题翻译：主机以太网适配器，用于在服务器环境中进行网络卸载
公开(公告)号：US07586936B2
公开(公告)日：2009-09-08
申请号：US11097608
申请日：2005-04-01
申请人： Ravi Kumar Arimilli , Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Edward Fuhs , Satya Prakash Sharma , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
发明人： Ravi Kumar Arimilli , Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Edward Fuhs , Satya Prakash Sharma , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
IPC分类号： H04L12/66
CPC分类号： H04L12/413 , H04L12/40032 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/324
摘要： An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ethernet Adapter (HEA) is an integrated Ethernet adapter providing a new approach to Ethernet and TCP acceleration. A set of TCP/IP acceleration features have been introduced in a toolkit approach: Servers TCP/IP stacks use these accelerators when and as required. The interface between the server and the network interface controller has been streamlined by bypassing the PCI bus. The HEA supports network virtualization. The HEA can be shared by multiple OSs providing the essential isolation and protection without affecting its performance.
摘要翻译：公开了一种以太网适配器。以太网适配器包括多个层，用于允许适配器从处理器接收和发送分组。多个层包括多路分解机制以允许处理器的划分。主机以太网适配器（HEA）是集成的以太网适配器，为以太网和TCP加速提供了新的方法。一组TCP / IP加速功能已经在工具包方法中引入：服务器TCP / IP堆栈在需要时使用这些加速器。服务器和网络接口控制器之间的接口通过绕过PCI总线进行了简化。 HEA支持网络虚拟化。 HEA可以由多个操作系统共享，提供基本的隔离和保护，而不会影响其性能。

15. 发明授权

US07508771B2 Method for reducing latency in a host ethernet adapter (HEA) 失效
标题翻译：用于减少主机以太网适配器（HEA）中的延迟的方法
公开(公告)号：US07508771B2
公开(公告)日：2009-03-24
申请号：US11096353
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04L12/26
CPC分类号： H04L12/413 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/324
摘要： A method for reducing latency in a host Ethernet adapter (HEA) includes the following. First, the HEA receives a packet with an internet protocol (IP) header and data in the HEA. The HEA parses a connection identifier from the IP header and accesses a negative cache in the HEA to determine if the connection identifier is not in a memory external to the HEA. The HEA applies a default treatment to the packet if the connection identifier is not in the memory, thereby reducing latency by decreasing access to the memory.
摘要翻译：一种用于减少主机以太网适配器（HEA）中的延迟的方法包括以下。首先，HEA在HEA中接收到具有互联网协议（IP）头部和数据的分组。 HEA从IP头解析连接标识符，并访问HEA中的负缓存，以确定连接标识符是否不在HEA外部的存储器中。如果连接标识符不在存储器中，则HEA对数据包应用默认处理，从而通过减少对存储器的访问来减少延迟。

16. 发明授权

US07492771B2 Method for performing a packet header lookup 失效
标题翻译：执行分组报头查找的方法
公开(公告)号：US07492771B2
公开(公告)日：2009-02-17
申请号：US11096362
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
IPC分类号： H04L12/56
CPC分类号： H04L49/3009 , H04L45/742 , H04L49/25
摘要： A method for performing a lookup for a packet in a computer network are disclosed. The packet includes a header. The method includes providing a parser, providing a lookup engine coupled with the parser, and providing a processor coupled with the lookup engine. The parser is for parsing the packet for the header prior to receipt of the packet being completed. The lookup engine performs a lookup for the header and returns a resultant. In one aspect, the lookup includes performing a local lookup of a cache that includes resultants of previous lookups. The processor processes the resultant.
摘要翻译：公开了一种用于在计算机网络中执行查找分组的方法。分组包括报头。该方法包括提供解析器，提供与解析器耦合的查找引擎，以及提供与查找引擎耦合的处理器。解析器用于在接收到完成的数据包之前解析报头的数据包。查找引擎对标题执行查找并返回结果。在一个方面，查找包括执行包括先前查找的结果的高速缓存的本地查找。处理器处理结果。

17. 发明授权

US07409520B2 Systems and methods for time division multiplex multithreading 失效
标题翻译：时分复用多线程的系统和方法
公开(公告)号：US07409520B2
公开(公告)日：2008-08-05
申请号：US11042692
申请日：2005-01-25
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

18. 发明申请

US20080147995A1 SYSTEMS AND METHODS FOR MULTI-FRAME CONTROL BLOCKS 有权
标题翻译：多框控制块的系统和方法
公开(公告)号：US20080147995A1
公开(公告)日：2008-06-19
申请号：US12039304
申请日：2008-02-28
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译：公开了一种用于在网络处理器中实现多帧控制块的系统和方法。实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

19. 发明授权

US07953951B2 Systems and methods for time division multiplex multithreading 失效
标题翻译：时分复用多线程的系统和方法
公开(公告)号：US07953951B2
公开(公告)日：2011-05-31
申请号：US12124396
申请日：2008-05-21
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

20. 发明授权

US07603539B2 Systems and methods for multi-frame control blocks 有权
标题翻译：多帧控制块的系统和方法
公开(公告)号：US07603539B2
公开(公告)日：2009-10-13
申请号：US12039304
申请日：2008-02-28
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译：公开了一种用于在网络处理器中实现多帧控制块的系统和方法。实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

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