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11. 发明授权

US07453133B2 Silicide/semiconductor structure and method of fabrication 有权
标题翻译：硅化物/半导体结构及其制造方法
公开(公告)号：US07453133B2
公开(公告)日：2008-11-18
申请号：US10880992
申请日：2004-06-30
申请人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
发明人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L27/095
CPC分类号： H01L23/3192 , H01L23/485 , H01L29/161 , H01L29/165 , H01L29/47 , H01L29/665 , H01L29/66628 , H01L29/7834 , H01L2924/0002 , H01L2924/19041 , H01L2924/3025 , H01L2924/00
摘要： A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.
摘要翻译：本发明的优选实施方案包括介电/金属/第二能带隙（E />）半导体/第一电极 g 衬底结构。为了降低接触电阻，将具有较低能量带隙（2Ω）的半导体与金属接触。第二个和第二个半导体的能带隙比第一个第二半导体的能量带隙低，半导体，优选低于1.1eV。此外，可以在金属上沉积介电层。电介质层具有内置应力以补偿金属，第二和第二半导体中的应力， g 衬底。还公开了制造该结构的过程。

12. 发明授权

US07045836B2 Semiconductor structure having a strained region and a method of fabricating same 有权
公开(公告)号：US07045836B2
公开(公告)日：2006-05-16
申请号：US10657616
申请日：2003-09-08
申请人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
发明人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L21/00
CPC分类号： H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/76232 , H01L21/823412 , H01L29/1054 , H01L29/66651
摘要： A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

13. 发明授权

US06902965B2 Strained silicon structure 有权
标题翻译：应变硅结构
公开(公告)号：US06902965B2
公开(公告)日：2005-06-07
申请号：US10699574
申请日：2003-10-31
申请人： Chung-Hu Ge , Wen-Chin Lee , Chenming Hu
发明人： Chung-Hu Ge , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/02 , H01L21/20 , H01L21/336 , H01L21/338 , H01L21/762 , H01L21/8238 , H01L29/08 , H01L29/10 , H01L29/74 , H01L29/78 , H01L31/0328 , H01L31/072
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823878 , H01L29/1054 , H01L29/6659 , H01L29/7833 , H01L29/7842
摘要： A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at lease part of the first trench, and the second trench is at least partially filled with an insulating material.
摘要翻译：半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。第一外延层形成在基板上。第一层相对于基底具有晶格失配。第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。因此，第三层可以是应变硅。第一沟槽延伸穿过第一层。第二沟槽延伸穿过第三层并且至少部分地穿过第二层。第二沟槽的至少一部分与第一沟槽的至少部分对准，并且第二沟槽至少部分地填充有绝缘材料。

14. 发明授权

US07495267B2 Semiconductor structure having a strained region and a method of fabricating same 有权
标题翻译：具有应变区域的半导体结构及其制造方法
公开(公告)号：US07495267B2
公开(公告)日：2009-02-24
申请号：US11409405
申请日：2006-04-21
申请人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
发明人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L31/0368
CPC分类号： H01L29/78 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/76232 , H01L29/7846
摘要： A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.
摘要翻译：包括适用于制造应变通道晶体管的高应变选择性外延顶层的半导体结构。顶层沉积在一系列一个或多个下层的最上面。每个层的晶格与其下层的晶格不匹配，其量不小于该系列的最低层与其所在的衬底之间的晶格失配。沟槽形成在最上层的层中。沟槽具有圆角，使得填充沟槽的电介质材料符合圆角。通过在沟槽形成之后加热最上面的串联层来产生圆角。

15. 发明授权

US07208754B2 Strained silicon structure 有权
标题翻译：应变硅结构
公开(公告)号：US07208754B2
公开(公告)日：2007-04-24
申请号：US11114981
申请日：2005-04-26
申请人： Chung-Hu Ge , Wen-Chin Lee , Chenming Hu
发明人： Chung-Hu Ge , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L29/06
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823878 , H01L29/1054 , H01L29/6659 , H01L29/7833 , H01L29/7842
摘要： A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.
摘要翻译：半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。第一外延层形成在基板上。第一层相对于衬底具有晶格失配。第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。因此，第三层可以是应变硅。第一沟槽延伸穿过第一层。第二沟槽延伸穿过第三层并且至少部分地穿过第二层。所述第二沟槽的至少一部分与所述第一沟槽的至少一部分对准，并且所述第二沟槽至少部分地填充有绝缘材料。

16. 发明申请

US20050023576A1 Semiconductor structure having a strained region and a method of fabricating same 有权
标题翻译：具有应变区域的半导体结构及其制造方法
公开(公告)号：US20050023576A1
公开(公告)日：2005-02-03
申请号：US10657616
申请日：2003-09-08
申请人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
发明人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L21/20 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L29/10 , H01L29/76 , H01L31/062 , H01L31/119
CPC分类号： H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/76232 , H01L21/823412 , H01L29/1054 , H01L29/66651
摘要： A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.
摘要翻译：包括适用于制造应变通道晶体管的高应变选择性外延顶层的半导体结构。顶层沉积在一系列一个或多个下层的最上面。每个层的晶格与其下层的晶格不匹配，其量不小于该系列的最低层与其所在的衬底之间的晶格失配。沟槽形成在最上层的层中。沟槽具有圆角，使得填充沟槽的电介质材料符合圆角。通过在沟槽形成之后加热最上面的串联层来产生圆角。

17. 发明授权

US06867433B2 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors 有权
标题翻译：包含应变通道部分耗尽，完全耗尽和多栅极晶体管的绝缘体上半导体芯片
公开(公告)号：US06867433B2
公开(公告)日：2005-03-15
申请号：US10426566
申请日：2003-04-30
申请人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7854
摘要： In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
摘要翻译：根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。

18. 发明申请

US20050233552A1 Strained channel on insulator device 失效
公开(公告)号：US20050233552A1
公开(公告)日：2005-10-20
申请号：US11083537
申请日：2005-03-18
申请人： Chung-Hu Ke , Chao-Hsiung Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
发明人： Chung-Hu Ke , Chao-Hsiung Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/00 , H01L21/30 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/02 , H01L29/72 , H01L29/772
CPC分类号： H01L21/823807 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/7848
摘要： A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

19. 发明申请

US20050093067A1 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors 有权
公开(公告)号：US20050093067A1
公开(公告)日：2005-05-05
申请号：US10999564
申请日：2004-11-29
申请人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7854
摘要： In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

20. 发明授权

US07268024B2 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors 有权
标题翻译：包含应变通道部分耗尽，完全耗尽和多栅极晶体管的绝缘体上半导体芯片
公开(公告)号：US07268024B2
公开(公告)日：2007-09-11
申请号：US10999564
申请日：2004-11-29
申请人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7854
摘要： In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
摘要翻译：根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。

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