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11. 发明授权

US08835309B2 Forming nickel—platinum alloy self-aligned silicide contacts 有权
标题翻译：形成镍 - 铂合金自对准硅化物触点
公开(公告)号：US08835309B2
公开(公告)日：2014-09-16
申请号：US13613579
申请日：2012-09-13
申请人： David F. Hilscher , Christian Lavoie , Ahmet S. Ozcan
发明人： David F. Hilscher , Christian Lavoie , Ahmet S. Ozcan
IPC分类号： H01L21/4763 , H01L21/44 , H01L31/00 , H01L23/48
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.
摘要翻译：执行硅化物接触工艺的方法包括在半导体器件结构上形成镍 - 铂合金（NiPt）层; 执行第一快速热退火（RTA），以使NiPt层的与半导体器件结构的半导体区域接触的部分反应，由此形成富金属硅化物区域; 执行第一湿蚀刻以去除至少NiPt层的未反应部分的镍组分; 使用包含硝酸（HNO 3），盐酸（HCl）和水（H 2 O）的稀释Aqua Regia处理进行第二次湿蚀刻以从NiPt层的未反应部分去除任何残余的铂材料; 并且在稀释的Aqua Regia处理之后，执行第二个RTA从富金属硅化物区形成最终的硅化物接触区。

12. 发明申请

US20120190192A1 Metal-Semiconductor Intermixed Regions 有权
公开(公告)号：US20120190192A1
公开(公告)日：2012-07-26
申请号：US13012043
申请日：2011-01-24
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/44
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

13. 发明申请

US20120181697A1 METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE 有权
标题翻译：控制金属半导体微结构的方法
公开(公告)号：US20120181697A1
公开(公告)日：2012-07-19
申请号：US13006664
申请日：2011-01-14
申请人： Christian Lavoie , Ahmet S. Ozcan , Zhen Zhang , Bin Yang
发明人： Christian Lavoie , Ahmet S. Ozcan , Zhen Zhang , Bin Yang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/768 , H01L21/28518 , H01L23/485 , H01L29/456 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.
摘要翻译：一种形成金属半导体合金的方法，其包括在半导体衬底的第一深度上形成混合金属半导体区域而没有热扩散。将混合后的金属半导体区域退火以形成织构化的金属半导体合金。在纹理金属半导体合金上形成第二金属层。纹理金属半导体合金上的第二金属层然后退火以形成金属半导体合金接触，其中来自第二金属层的金属元素通过织构化金属半导体合金扩散以提供模板化的金属半导体合金。模板化金属半导体合金的厚度范围为15nm〜50nm的金属半导体合金的晶粒尺寸大于2×。

14. 发明授权

US08021971B2 Structure and method to form a thermally stable silicide in narrow dimension gate stacks 有权
标题翻译：在窄尺寸栅极堆叠中形成热稳定的硅化物的结构和方法
公开(公告)号：US08021971B2
公开(公告)日：2011-09-20
申请号：US12611946
申请日：2009-11-04
申请人： Anthony G. Domenicucci , Christian Lavoie , Ahmet S. Ozcan
发明人： Anthony G. Domenicucci , Christian Lavoie , Ahmet S. Ozcan
IPC分类号： H01L21/3205 , H01L29/861
CPC分类号： H01L29/7833 , H01L21/28052 , H01L21/28114 , H01L29/42376 , H01L29/66507 , H01L29/6653 , H01L29/6659
摘要： An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height.
摘要翻译：提供了一种集成电路，其包括具有小于或等于65nm的宽度的窄栅极堆叠，其包括硅化物区域，该硅化物区域包含偏离硅化物的区域的硅离子，所述硅化物区域远离硅化物的顶表面并朝向由硅化物的顶表面限定的下部分在栅极导体的侧壁上的间隔物的下拉高度。在优选实施例中，在形成硅化物之前，将间隔物拉下。硅化物首先通过在250℃至450℃的温度下的地层退火形成。随后，在450℃至550℃的温度下进行偏析退火.Pt 沿着硅化物层的垂直长度在分离区域内具有峰值Pt浓度，并且偏析的Pt区域的峰值Pt浓度的一半的宽度小于硅化物层的顶表面与硅化物层的顶表面之间的距离的50％下拉垫片高度。

15. 发明申请

US20110101472A1 STRUCTURE AND METHOD TO FORM A THERMALLY STABLE SILICIDE IN NARROW DIMENSION GATE STACKS 有权
标题翻译：在窄尺寸门架中形成热稳定的硅酮的结构和方法
公开(公告)号：US20110101472A1
公开(公告)日：2011-05-05
申请号：US12611946
申请日：2009-11-04
申请人： Anthony G. Domenicucci , Christian Lavoie , Ahmet S. Ozcan
发明人： Anthony G. Domenicucci , Christian Lavoie , Ahmet S. Ozcan
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L29/7833 , H01L21/28052 , H01L21/28114 , H01L29/42376 , H01L29/66507 , H01L29/6653 , H01L29/6659
摘要： An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height.
摘要翻译：提供了一种集成电路，其包括具有小于或等于65nm的宽度的窄栅极堆叠，其包括硅化物区域，该硅化物区域包含偏离硅化物的区域的硅离子，所述硅化物区域远离硅化物的顶表面并朝向由硅化物的顶表面限定的下部分在栅极导体的侧壁上的间隔物的下拉高度。在优选实施例中，在形成硅化物之前，将间隔物拉下。硅化物首先通过在250℃至450℃的温度下的地层退火形成。随后，在450℃至550℃的温度下进行偏析退火.Pt 沿着硅化物层的垂直长度在分离区域内具有峰值Pt浓度，并且偏析的Pt区域的峰值Pt浓度的一半的宽度小于硅化物层的顶表面与硅化物层的顶表面之间的距离的50％下拉垫片高度。

16. 发明申请

US20130020616A1 SILICIDED DEVICE WITH SHALLOW IMPURITY REGIONS AT INTERFACE BETWEEN SILICIDE AND STRESSED LINER 失效
标题翻译：在硅胶和压力衬里之间的界面处具有较小的污染区域的硅化物
公开(公告)号：US20130020616A1
公开(公告)日：2013-01-24
申请号：US13186587
申请日：2011-07-20
申请人： Javier Ayala , Christian Lavoie , Ahmet S. Ozcan
发明人： Javier Ayala , Christian Lavoie , Ahmet S. Ozcan
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/7843 , H01L21/265 , H01L21/28052 , H01L21/823418 , H01L29/665
摘要： A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.
摘要翻译：形成半导体器件的方法包括形成场效应晶体管（FET）的硅化物接触区域; 在硅化物接触区的顶表面中形成浅杂质区; 以及在所述FET上形成应力衬垫，使得所述浅杂质区位于所述硅化物接触区域和所述受应力衬垫之间的界面处，其中所述浅杂质区域包括一种或多种杂质，并且被配置为阻止所述硅的扩散硅化物接触区域，并防止硅化物接触区域的形态退化。

17. 发明申请

US20120295439A1 Metal-Semiconductor Intermixed Regions 审中-公开
标题翻译：金属半导体混合区域
公开(公告)号：US20120295439A1
公开(公告)日：2012-11-22
申请号：US13564181
申请日：2012-08-01
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.
摘要翻译：在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层，第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

18. 发明申请

US20110001169A1 FORMING UNIFORM SILICIDE ON 3D STRUCTURES 审中-公开
标题翻译：在三维结构上形成均匀的硅化物
公开(公告)号：US20110001169A1
公开(公告)日：2011-01-06
申请号：US12495989
申请日：2009-07-01
申请人： Ahmet S. Ozcan , Christian Lavoie
发明人： Ahmet S. Ozcan , Christian Lavoie
IPC分类号： H01L29/49 , H01L21/3205
CPC分类号： H01L29/41791 , H01L21/28518 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： By using a non-conformal diffusion barrier in conjunction with a similarly deposited non-conformal initial deposition of siliciding material, a substantially uniform and conformal silicide can be formed in a 3D structure such as the fin of a FinFET. The siliciding material may be nickel (Ni), the diffusion barrier may be titanium (Ti) or titanium nitride (TiN). Generally, the diffusion barrier may be any material which will inhibit, but not block, diffusion of the siliciding material into the silicon. In this manner, a non-conformal barrier deposition, in conjunction with a non-conformal silicide material deposition, after anneal, results in substantially conformal silicide formation.
摘要翻译：通过使用非共形扩散势垒结合同样沉积的非保形的硅化物材料的初始沉积，可以在诸如FinFET的鳍的3D结构中形成基本上均匀且适形的硅化物。硅化物可以是镍（Ni），扩散阻挡层可以是钛（Ti）或氮化钛（TiN）。通常，扩散阻挡层可以是将硅化物扩散到硅中的任何材料。以这种方式，在非退火之后，结合非保形硅化物材料沉积的非保形阻挡层沉积导致基本上保形的硅化物形成。

19. 发明申请

US20130069124A1 MOSFET INTEGRATED CIRCUIT WITH UNIFORMLY THIN SILICIDE LAYER AND METHODS FOR ITS MANUFACTURE 有权
标题翻译：具有均匀薄膜硅层的MOSFET集成电路及其制造方法
公开(公告)号：US20130069124A1
公开(公告)日：2013-03-21
申请号：US13237732
申请日：2011-09-20
申请人： Bin Yang , Christian Lavoie , Emre Alptekin , Ahmet S. Ozcan , Cung D. Tran , Mark Raymond
发明人： Bin Yang , Christian Lavoie , Emre Alptekin , Ahmet S. Ozcan , Cung D. Tran , Mark Raymond
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/6659 , H01L29/7833
摘要： An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.
摘要翻译：提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。在金属/硅界面处形成均匀薄的无定形混合合金层时，除去过量的（未反应的）金属。该器件被退火以促进在衬底表面上形成薄的硅化物层，其在宽和窄接触沟槽的底部显示均匀的厚度。

20. 发明授权

US08349716B2 Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device 失效
标题翻译：具有减小的结漏电的半导体器件和形成这种半导体器件的相关方法
公开(公告)号：US08349716B2
公开(公告)日：2013-01-08
申请号：US12911186
申请日：2010-10-25
申请人： Ming Cai , Christian Lavoie , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Ming Cai , Christian Lavoie , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/336 , H01L21/04
CPC分类号： H01L21/2257 , H01L21/28512 , H01L21/28518 , H01L29/665 , H01L29/66643
摘要： Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.
摘要翻译：公开了一种具有p-n结的半导体器件，其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。具体地说，形成具有p-n结的半导体层。在半导体层上形成金属硅化物层，并且将掺杂剂注入到金属硅化物层中。执行退火处理，使掺杂剂朝向金属硅化物半导体层界面迁移，使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。结果，硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度，这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

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