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11. 发明授权

US08330198B2 Device for preventing current-leakage 有权
标题翻译：防止漏电的装置
公开(公告)号：US08330198B2
公开(公告)日：2012-12-11
申请号：US12758252
申请日：2010-04-12
申请人： Shin Bin Huang , Chung-Lin Huang , Ching-Nan Hsiao , Tzung Han Lee
发明人： Shin Bin Huang , Chung-Lin Huang , Ching-Nan Hsiao , Tzung Han Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/0259
摘要： A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem.
摘要翻译：用于防止漏电的装置位于存储单元的晶体管和电容器之间。用于防止漏电的装置的两个端子分别与晶体管的从端和电容器的电极连接。用于防止漏电的装置具有至少两个p-n结。用于防止漏电的装置是侧向可控硅整流器，用于交流电流的二极管或可控硅整流器。通过利用用于防止漏电的装置的驱动特性，存储在电容器中的电荷几乎不会通过用于防止晶体管截止时漏电的装置，从而改善漏电问题。

12. 发明授权

US07981743B2 Method of fabricating a memory cell 有权
标题翻译：制造存储单元的方法
公开(公告)号：US07981743B2
公开(公告)日：2011-07-19
申请号：US12039744
申请日：2008-02-29
申请人： Mao-Quan Chen , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Mao-Quan Chen , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/336 , H01L21/302 , H01L21/461
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568
摘要： The memory cell of the present invention has two independent storage regions embedded into two opposite sidewalls of the control gate respectively. In this way, the data storage can be more reliable. Other features of the present invention are that the thickness of the dielectric layers is different, and the two independent storage regions are formed on opposite bottom sides of the opening by the etching process and form a shape like a spacer. The advantage of the aforementioned method is that the fabricating process is simplified and the difficulty of self-alignment is reduced.
摘要翻译：本发明的存储单元具有分别嵌入控制门的两个相对的侧壁中的两个独立的存储区域。以这种方式，数据存储可以更可靠。本发明的其他特征是电介质层的厚度不同，并且两个独立的存储区域通过蚀刻工艺形成在开口的相对的底侧上并形成像间隔物的形状。上述方法的优点是简化了制造工艺，并且减少了自对准的难度。

13. 发明申请

US20100279472A1 MANUFACTURING METHOD OF NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的制造方法
公开(公告)号：US20100279472A1
公开(公告)日：2010-11-04
申请号：US12838495
申请日：2010-07-19
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/8239
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.
摘要翻译：在非易失性存储器的制造方法中，提供衬底，并且在衬底中形成条形隔离结构。包括存储单元列的第一存储器阵列形成在衬底上。每个存储单元列包括彼此串联连接的存储器单元，设置在存储单元外部的衬底中的源极/漏极区域，设置在源极/漏极区域和存储器单元之间的选择晶体管，跨过存储器单元延伸的控制栅极线列和第二方向，并且首先选择分别连接第二方向上的选择晶体管的栅极线。第一触点形成在第一存储器阵列的一侧的基板上，并沿第二方向布置。每个第一接触件在每两个相邻有效区域中连接源极/漏极区域。

14. 发明授权

US07713820B2 Method for manufacturing non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US07713820B2
公开(公告)日：2010-05-11
申请号：US11945199
申请日：2007-11-26
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/7887 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.
摘要翻译：提供一种用于制造非易失性存储器的方法。在衬底中形成的沟槽中形成隔离结构。去除隔离结构的一部分以形成凹部。在基板上依次形成第一介电层和第一导电层。在基板上形成棒状盖层。未被棒状帽层覆盖的第一导电层被去除以形成第一栅极结构。在第一栅极结构的侧壁上形成第二介电层。在第一栅极结构之间的衬底上形成第三电介质层。在第三电介质层上形成第二导电层。条形盖层和第一导电层的一部分被去除以形成第二栅极结构。在每个第二栅极结构的两侧在衬底中形成掺杂区域。

15. 发明申请

US20090032858A1 LAYOUT AND STRUCTURE OF MEMORY 有权
标题翻译：存储器的布局和结构
公开(公告)号：US20090032858A1
公开(公告)日：2009-02-05
申请号：US11927616
申请日：2007-10-29
申请人： Shin-Bin Huang , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Shin-Bin Huang , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.
摘要翻译：提供闪存。具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅极晶体管的选择栅极的栅极导体线之间的空间。因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。耗尽模式的选择栅晶体管总是导通。

16. 发明授权

US08105900B2 Manufacturing method of non-volatile memory 有权
标题翻译：非易失性存储器的制造方法
公开(公告)号：US08105900B2
公开(公告)日：2012-01-31
申请号：US12838495
申请日：2010-07-19
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.
摘要翻译：在非易失性存储器的制造方法中，提供衬底，并且在衬底中形成条形隔离结构。包括存储单元列的第一存储器阵列形成在衬底上。每个存储单元列包括彼此串联连接的存储器单元，设置在存储单元外部的衬底中的源极/漏极区域，设置在源极/漏极区域和存储器单元之间的选择晶体管，跨越存储器单元延伸的控制栅极线列和第二方向，并且首先选择分别连接第二方向上的选择晶体管的栅极线。第一触点形成在第一存储器阵列的一侧的基板上，并沿第二方向布置。每个第一接触件在每两个相邻有效区域中连接源极/漏极区域。

17. 发明授权

US07642191B2 Method of forming semiconductor structure 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07642191B2
公开(公告)日：2010-01-05
申请号：US12019260
申请日：2008-01-24
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/311
CPC分类号： H01L21/823481 , H01L21/823437 , H01L27/115 , H01L27/11521
摘要： A method of forming a semiconductor structure is provided. The method includes providing a substrate and forming a mask layer on the substrate, Next, dielectric isolations are formed in the mask layer and the substrate, wherein the dielectric isolations extend above the substrate. Then, the mask layer is removed to expose a portion of the substrate, and a dielectric layer is formed on the exposed portion of the substrate. Subsequently, a first conductive layer is formed on the dielectric layer, and a portion of the dielectric isolation is removed, wherein a top surface of the remaining dielectric isolation is lower than a top surface of the first conductive layer. Moreover, a conformal layer is formed over the substrate, and a second conductive layer is formed on the conformal layer.
摘要翻译：提供一种形成半导体结构的方法。该方法包括提供衬底并在衬底上形成掩模层。接下来，在掩模层和衬底中形成介电隔离，其中介电隔离物延伸到衬底上方。然后，去除掩模层以露出衬底的一部分，并且在衬底的暴露部分上形成电介质层。随后，在电介质层上形成第一导电层，去除介电隔离的一部分，其中绝缘隔离的顶表面低于第一导电层的顶表面。此外，在衬底上形成保形层，并且在保形层上形成第二导电层。

18. 发明申请

US20090087975A1 METHOD FOR MANUFACTURING A MEMORY 有权
标题翻译：制造存储器的方法
公开(公告)号：US20090087975A1
公开(公告)日：2009-04-02
申请号：US12018209
申请日：2008-01-23
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L21/3205
CPC分类号： H01L27/11521
摘要： A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.
摘要翻译：一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

19. 发明申请

US20090087544A1 METHOD OF FABRICATING A MEMORY CELL 有权
标题翻译：制造记忆细胞的方法
公开(公告)号：US20090087544A1
公开(公告)日：2009-04-02
申请号：US12039744
申请日：2008-02-29
申请人： Mao-Quan Chen , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Mao-Quan Chen , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： B05D5/12
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568
摘要： The memory cell of the present invention has two independent storage regions embedded into two opposite sidewalls of the control gate respectively. In this way, the data storage can be more reliable. Other features of the present invention are that the thickness of the dielectric layers is different, and the two independent storage regions are formed on opposite bottom sides of the opening by the etching process and form a shape like a spacer. The advantage of the aforementioned method is that the fabricating process is simplified and the difficulty of self-alignment is reduced.
摘要翻译：本发明的存储单元具有分别嵌入控制门的两个相对的侧壁中的两个独立的存储区域。以这种方式，数据存储可以更可靠。本发明的其他特征是电介质层的厚度不同，并且两个独立的存储区域通过蚀刻工艺形成在开口的相对的底侧上并形成像间隔物的形状。上述方法的优点是简化了制造工艺，并且减少了自对准的难度。

20. 发明申请

US20090065846A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20090065846A1
公开(公告)日：2009-03-12
申请号：US11955396
申请日：2007-12-13
申请人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
发明人： Hung-Mine Tsai , Ching-Nan Hsiao , Chung-Lin Huang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/7887
摘要： A manufacturing method of a non-volatile memory includes forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate to form first gate structures; conformally forming a second dielectric layer on the substrate; forming a first spacer having a larger wet etching rate than the second dielectric layer on each sidewall of each first gate structure; partially removing the first and second dielectric layers to expose the substrate. A third dielectric layer is formed on the substrate between the first gate structures; removing the first spacer; forming a second conductive layer on the third dielectric layer; removing the first cap layer and a portion of the first conductive layer to form second gate structures; and forming doped regions in the substrate at two sides of each second gate structure.
摘要翻译：非易失性存储器的制造方法包括在衬底上依次形成第一电介质层，第一导电层和第一覆盖层，以形成第一栅极结构; 在基底上保形地形成第二电介质层; 在每个第一栅极结构的每个侧壁上形成具有比第二介电层更大的湿蚀刻速率的第一间隔物; 部分地去除第一和第二电介质层以暴露衬底。在第一栅极结构之间的衬底上形成第三电介质层; 去除第一间隔物; 在所述第三介电层上形成第二导电层; 移除所述第一盖层和所述第一导电层的一部分以形成第二栅极结构; 以及在每个第二栅极结构的两侧在衬底中形成掺杂区域。

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