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11. 发明授权

US07825034B2 Method of fabricating openings and contact holes 有权
标题翻译：制造开口和接触孔的方法
公开(公告)号：US07825034B2
公开(公告)日：2010-11-02
申请号：US11163149
申请日：2005-10-06
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the etch stop layer. The dielectric thin film disposed on the dielectric layer and the etch stop layer is then removed.
摘要翻译：提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的衬底。然后将电介质层图案化以形成露出蚀刻停止层的多个开口。随后形成介电薄膜以覆盖电介质层，开口的侧壁和蚀刻停止层。然后去除设置在电介质层和蚀刻停止层上的电介质薄膜。

12. 发明授权

US07817265B2 Alignment mark and defect inspection method 有权
标题翻译：校准标记和缺陷检查方法
公开(公告)号：US07817265B2
公开(公告)日：2010-10-19
申请号：US12237404
申请日：2008-09-25
申请人： Ling-Chun Chou , Ming-Tsung Chen , Hsi-Hua Liu , Shuen-Cheng Lei , Po-Chao Tsao
发明人： Ling-Chun Chou , Ming-Tsung Chen , Hsi-Hua Liu , Shuen-Cheng Lei , Po-Chao Tsao
IPC分类号： G01N21/00
CPC分类号： G03F7/70658 , G03F7/70633 , G03F7/7065 , G03F9/7076 , H01L22/12 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A defect inspection method is disclosed. A first type defect inspection system is used to perform a first defect inspection by aligning to an alignment mark on a wafer as a reference point for the first defect inspection. A fabrication process is performed on the wafer thereafter, and a second defect inspection is performed by using a second type defect inspection system to align the alignment mark on the wafer as the reference point for the second defect inspection.
摘要翻译：公开了一种缺陷检查方法。第一种缺陷检查系统用于通过与晶片上的对准标记对准来进行第一缺陷检查，作为第一缺陷检查的参考点。然后在晶片上进行制造工艺，并且通过使用第二类型缺陷检查系统来执行第二缺陷检查，以使晶片上的对准标记作为第二缺陷检查的参考点。

13. 发明授权

US07759742B2 Metal oxide semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管
公开(公告)号：US07759742B2
公开(公告)日：2010-07-20
申请号：US11691485
申请日：2007-03-26
申请人： Ming-Tsung Chen , Chang-Chi Huang , Po-Chao Tsao
发明人： Ming-Tsung Chen , Chang-Chi Huang , Po-Chao Tsao
IPC分类号： H01L29/76
CPC分类号： H01L21/28518 , H01L21/26506 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/7834
摘要： A metal oxide semiconductor (MOS) transistor is disclosed. The MOS transistor includes: a semiconductor substrate; a gate disposed on the semiconductor substrate, wherein the gate comprises two sidewalls; a spacer formed on the sidewalls of the gate; a source/drain region disposed in the semiconductor substrate; a silicide layer disposed on top of the gate and the surface of the source/drain region; and a retarded interface layer disposed in the junction between the silicide layer and the gate and source/drain region.
摘要翻译：公开了一种金属氧化物半导体（MOS）晶体管。 MOS晶体管包括：半导体衬底; 设置在所述半导体衬底上的栅极，其中所述栅极包括两个侧壁; 形成在栅极的侧壁上的间隔物; 设置在所述半导体衬底中的源/漏区; 设置在栅极的顶部和源极/漏极区域的表面上的硅化物层; 以及设置在硅化物层与栅极和源极/漏极区之间的结中的延迟界面层。

14. 发明授权

US07105412B1 Silicide process utilizing pre-amorphization implant and second spacer 有权
标题翻译：使用前非晶化植入物和第二间隔物的硅化物工艺
公开(公告)号：US07105412B1
公开(公告)日：2006-09-12
申请号：US10907126
申请日：2005-03-22
申请人： Ming-Tsung Chen
发明人： Ming-Tsung Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A gate electrode is formed on a substrate with a gate insulating layer therebetween. A liner is then deposited on sidewalls of the gate electrode. Source/drain extensions are implanted into the substrate. A first spacer is then formed on the liner. Deep source/drain are implanted into the substrate. A second spacer is formed at the foot of the first spacer. A tilt-angle pre-amorphization implant (PAI) is conducted to form an amorphized layer next to the second spacer. A metal layer is then sputtered on the amorphized layer. The metal layer reacts with the amorphized layer to form a metal silicide layer thereto.
摘要翻译：栅电极形成在基板上，栅极绝缘层在其间。然后将衬垫沉积在栅电极的侧壁上。源极/漏极延伸部分植入到衬底中。然后在衬套上形成第一间隔件。将深源极/漏极注入到衬底中。第二间隔件形成在第一间隔件的底部。进行倾斜角度前非晶化植入（PAI）以在第二间隔物旁边形成非晶化层。然后将金属层溅射在非晶化层上。金属层与非晶化层反应以形成金属硅化物层。

15. 发明授权

US11228177B2 Power control system 有权
公开(公告)号：US11228177B2
公开(公告)日：2022-01-18
申请号：US16824847
申请日：2020-03-20
申请人： Ming-Tsung Chen
发明人： Ming-Tsung Chen
IPC分类号： H02J3/32 , H02J13/00 , G05B13/02 , G01R21/133 , H02J3/38
摘要： A power control system is disposed in a predetermined area. The power control system includes a server, a smart gateway device, a power detection device, a smart meter, a first power control device, a power generation device, a second power control device, a plurality of electronic devices, and a power storage device. The power detection device detects a value of a supply current per second of the first power of the first power control device. The power detection device detects a value of a used current per second of the second power of the second power control device. The power detection device provides a current difference between the value of the supply current and the value of the used current to the first power control device and the smart gateway device. The first power control device adjusts the first power at least based on the current difference.

16. 发明授权

US09202914B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09202914B2
公开(公告)日：2015-12-01
申请号：US13419530
申请日：2012-03-14
申请人： Hsin-Ming Hou , Yu-Cheng Tung , Ji-Fu Kung , Wai-Yi Lien , Ming-Tsung Chen
发明人： Hsin-Ming Hou , Yu-Cheng Tung , Ji-Fu Kung , Wai-Yi Lien , Ming-Tsung Chen
IPC分类号： H01L29/78 , H01L21/336 , H01L31/072 , H01L29/12 , H01L21/762 , H01L29/66
CPC分类号： H01L29/78 , H01L21/76224 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.
摘要翻译：提供了包括衬底，多个隔离结构，至少栅极结构，多个虚拟栅极结构和多个外延结构的半导体器件。衬底具有由设置在衬底内的隔离结构限定的有源区域。也就是说，在隔离结构之间限定有源区。栅极结构设置在基板上并且位于有源区域内。虚拟栅极结构设置在基板上并且位于有源区域之外。每个虚拟栅极结构的边缘与有效区域的边界分开，距离小于135埃。外延结构被布置在栅极结构的两侧的有源区域内和衬底的一部分中。本发明还提供了一种制造半导体器件的方法。

17. 发明授权

US08518127B2 Solid capacitor and manufacturing method thereof 有权
标题翻译：固体电容器及其制造方法
公开(公告)号：US08518127B2
公开(公告)日：2013-08-27
申请号：US13176736
申请日：2011-07-05
申请人： Wei-Chih Lee , Ming-Tsung Chen
发明人： Wei-Chih Lee , Ming-Tsung Chen
IPC分类号： H01G9/00
CPC分类号： H01G9/15 , H01G9/0032 , H01G9/012 , H01G9/052 , H01G9/08
摘要： A manufacturing method of solid capacitors includes the following steps. First step is forming a plurality of separated adhesive layer on an insulating substrate. Next step is disposing valve-metal wires on the adhesive layers. Next step is forming a conductive layer on the adhesive layer and the valve-metal wires. Next step is forming a dielectric structure on the exposed surface of the valve-metal wires and the conductive layer. Next step is forming a hydrophobic layer and a conductive unit. Next step is separating the formed structures as individual capacitors. Next step is packaging the formed structures and forming terminals connected to the formed structures.
摘要翻译：固体电容器的制造方法包括以下步骤。第一步是在绝缘基板上形成多个分离的粘合剂层。下一步是将阀 - 金属丝布置在粘合剂层上。下一步是在粘合剂层和阀金属线上形成导电层。下一步是在阀 - 金属线和导电层的暴露表面上形成电介质结构。下一步是形成疏水层和导电单元。下一步是将形成的结构作为单独的电容器分离。下一步是包装形成的结构和形成连接到形成的结构的端子。

18. 发明授权

US08305734B2 Insulating encapsulation structure for solid chip electrolytic capacitor 有权
标题翻译：固体电解电容绝缘封装结构
公开(公告)号：US08305734B2
公开(公告)日：2012-11-06
申请号：US12907158
申请日：2010-10-19
申请人： Chi-Hao Chiu , Ming-Tsung Chen , Chiao-Yinms Yang
发明人： Chi-Hao Chiu , Ming-Tsung Chen , Chiao-Yinms Yang
IPC分类号： H01G9/08
CPC分类号： H01G9/15 , H01G9/08
摘要： An insulating encapsulation structure is applied to a chip type solid electrolytic capacitor that includes an aluminum metallic body having an aluminum core layer. An upper oxide film and a lower oxide film respectively having fine holes on their surfaces are respectively formed on the top and the bottom of the aluminum core layer. On side surfaces of the metallic body is a plurality of cut burrs. The upper oxide film and the lower oxide film of the metallic body are respectively separated by a separating layer to form an anode and a cathode. The insulating encapsulation structure includes an insulating cover layer enclosing an outer surface of the metallic body to cover the cut burrs. Thereby, the required chemical conversion process is reduced along with current leakage, the overall manufacturing cost is lowered, and the mechanical strength for the edge of the metallic body is reinforced.
摘要翻译：绝缘封装结构被应用于包括具有铝芯层的铝金属体的芯片型固体电解电容器。在铝芯层的顶部和底部分别形成表面上分别具有细孔的上氧化膜和低氧化膜。金属体的侧面是多个切割毛刺。金属体的上部氧化物膜和下部氧化物膜分别通过分离层分离以形成阳极和阴极。绝缘封装结构包括封闭金属体的外表面以覆盖切割毛刺的绝缘覆盖层。因此，随着电流泄漏，所需的化学转化过程减少，整体制造成本降低，并且增强了金属体边缘的机械强度。

19. 发明申请

US20110007452A1 Lamellar Stacked Solid Electrolytic Capacitor 有权
标题翻译：层状堆叠固体电解电容器
公开(公告)号：US20110007452A1
公开(公告)日：2011-01-13
申请号：US12713398
申请日：2010-02-26
申请人： Ching-Feng Lin , Yui-Hsin Fran , Chi-Hao Chiu , Ming-Tsung Chen , Cheng-Wei Lai , Chun-Chia Huang
发明人： Ching-Feng Lin , Yui-Hsin Fran , Chi-Hao Chiu , Ming-Tsung Chen , Cheng-Wei Lai , Chun-Chia Huang
IPC分类号： H01G9/15
CPC分类号： H01G9/012 , H01G2/06 , H01G9/15
摘要： A lamellar stacked solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit is composed of a negative foil, an isolation paper with conductive polymer substance, a positive foil, an isolation paper with conductive polymer substance and a negative foil that are stacked onto each other in sequence, the positive foils of the capacitor units are electrically connected to each other, the negative foils of the capacitor units are electrically connected to each other, and the positive foils and the negative foils are insulated from each other. The substrate unit has a positive guiding substrate electrically connected to the positive foils of the capacitor units and a negative guiding substrate electrically connected to the negative foils of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit.
摘要翻译：片状堆叠固体电解电容器包括多个电容器单元，基板单元和封装单元。每个电容器单元由负箔，具有导电聚合物物质的隔离纸，正箔，具有导电聚合物物质的隔离纸和负箔依次堆叠组成，电容器单元的正箔是彼此电连接，电容器单元的负箔彼此电连接，并且正箔和负箔彼此绝缘。基板单元具有电连接到电容器单元的正箔的正引导基板和电连接到电容器单元的负箔的负引导基板。封装单元覆盖电容器单元和衬底单元的一部分。

20. 发明申请

US20100073671A1 ALIGNMENT MARK AND DEFECT INSPECTION METHOD 有权
标题翻译：对准标记和缺陷检查方法
公开(公告)号：US20100073671A1
公开(公告)日：2010-03-25
申请号：US12237404
申请日：2008-09-25
申请人： Ling-Chun Chou , Ming-Tsung Chen , Hsi-Hua Liu , Shuen-Cheng Lei , Po-Chao Tsao
发明人： Ling-Chun Chou , Ming-Tsung Chen , Hsi-Hua Liu , Shuen-Cheng Lei , Po-Chao Tsao
IPC分类号： G01N21/88
CPC分类号： G03F7/70658 , G03F7/70633 , G03F7/7065 , G03F9/7076 , H01L22/12 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A defect inspection method is disclosed. A first type defect inspection system is used to perform a first defect inspection by aligning to an alignment mark on a wafer as a reference point for the first defect inspection. A fabrication process is performed on the wafer thereafter, and a second defect inspection is performed by using a second type defect inspection system to align the alignment mark on the wafer as the reference point for the second defect inspection.
摘要翻译：公开了一种缺陷检查方法。第一种缺陷检查系统用于通过与晶片上的对准标记对准来进行第一缺陷检查，作为第一缺陷检查的参考点。然后在晶片上进行制造工艺，并且通过使用第二类型缺陷检查系统来执行第二缺陷检查，以使晶片上的对准标记作为第二缺陷检查的参考点。

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