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11. 发明授权

US06696361B2 Post-CMP removal of surface contaminants from silicon wafer 有权
标题翻译： CMP后移除表面污染物
公开(公告)号：US06696361B2
公开(公告)日：2004-02-24
申请号：US09854006
申请日：2001-05-10
申请人： Shao-Chung Hu , Teng-Chun Tsai , Chia-Lin Hsu , Yung-Tsung Wei
发明人： Shao-Chung Hu , Teng-Chun Tsai , Chia-Lin Hsu , Yung-Tsung Wei
IPC分类号： H01L214763
CPC分类号： H01L21/02074 , H01L21/3212
摘要： A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.
摘要翻译：化学机械抛光（CMP）后从硅晶片去除污染物的方法。在铜化学机械抛光和随后的屏障化学 - 机械抛光操作之后，施加去离子水中的臭氧水溶液以清洁硅晶片，从而去除晶片上的污染物。或者，在铜和阻挡CMP之后进行臭氧/去离子水缓冲抛光工艺，然后使用化学溶液或去离子水清洁晶片。或者，在铜CMP和阻挡CMP两者之后进行臭氧/去离子水缓冲抛光工艺，然后使用化学溶液或去离子水清洁晶片。

12. 发明授权

US06616510B2 Chemical mechanical polishing method for copper 有权
公开(公告)号：US06616510B2
公开(公告)日：2003-09-09
申请号：US09735323
申请日：2000-12-12
申请人： Chia-Lin Hsu , Teng-Chun Tsai , Yung-Tsung Wei , Ming-Sheng Yang
发明人： Chia-Lin Hsu , Teng-Chun Tsai , Yung-Tsung Wei , Ming-Sheng Yang
IPC分类号： H01L21465
CPC分类号： H01L21/3212 , B24B37/044 , C09G1/02
摘要： A chemical-mechanical polishing method for polishing a copper oxide layer and a copper layer. The copper oxide layer above the copper layer is first polished using an aqueous solution having a high concentration of polishing particles/chelating agent. The copper layer is then polished using a polishing slurry having a low concentration of polishing particles/chelating agent or the polishing slurry free of polishing particles/chelating agent. Alternatively, the copper oxide layer is polished using a mixture of the aqueous solution and the polishing slurry. After the copper oxide layer is removed, the copper layer is polished using the polishing slurry alone.

13. 发明授权

US08802524B2 Method of manufacturing semiconductor device having metal gates 有权
标题翻译：制造具有金属栅极的半导体器件的方法
公开(公告)号：US08802524B2
公开(公告)日：2014-08-12
申请号：US13053223
申请日：2011-03-22
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
IPC分类号： H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.
摘要翻译：本发明提供一种制造具有金属栅极的半导体器件的方法。首先，提供基板。具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。去除第一牺牲栅极以形成第一沟槽。然后，在第一沟槽中形成第一金属层。去除第二牺牲栅极以形成第二沟槽。接下来，在第一沟槽和第二沟槽中形成第二金属层。最后，在第二金属层上形成第三金属层，其中第三金属层被填充到第一沟槽和第二沟槽中。

14. 发明授权

US08709910B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08709910B2
公开(公告)日：2014-04-29
申请号：US13459262
申请日：2012-04-30
申请人： Chin-I Liao , Chia-Lin Hsu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee , Min-Chung Cheng
发明人： Chin-I Liao , Chia-Lin Hsu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee , Min-Chung Cheng
IPC分类号： H01L21/76
CPC分类号： H01L21/0237 , H01L21/02532 , H01L21/02639 , H01L21/76224 , H01L29/66795
摘要： A semiconductor process includes the following steps. A semiconductor substrate is provided. The semiconductor substrate has a patterned isolation layer and the patterned isolation layer has an opening exposing a silicon area of the semiconductor substrate. A silicon rich layer is formed on the sidewalls of the opening. An epitaxial process is performed to form an epitaxial structure on the silicon area in the opening.
摘要翻译：半导体工艺包括以下步骤。提供半导体衬底。半导体衬底具有图案化隔离层，并且图案化隔离层具有暴露半导体衬底的硅区域的开口。在开口的侧壁上形成富硅层。执行外延工艺以在开口中的硅区域上形成外延结构。

15. 发明授权

US08643069B2 Semiconductor device having metal gate and manufacturing method thereof 有权
标题翻译：具有金属栅极的半导体器件及其制造方法
公开(公告)号：US08643069B2
公开(公告)日：2014-02-04
申请号：US13180556
申请日：2011-07-12
申请人： Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
发明人： Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
IPC分类号： H01L29/76 , H01L21/02
CPC分类号： H01L21/28008 , H01L21/28123 , H01L21/31053 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.
摘要翻译：具有金属栅极的半导体器件包括具有形成在其中的至少一个金属栅极的多个浅沟槽隔离物（STI）的基板，以及分别位于金属的两侧的至少一对辅助虚设结构门和衬底上。

16. 发明申请

US20130341638A1 MULTI-GATE FIELD-EFFECT TRANSISTOR AND PROCESS THEREOF 有权
标题翻译：多栅极场效应晶体管及其工艺
公开(公告)号：US20130341638A1
公开(公告)日：2013-12-26
申请号：US13530127
申请日：2012-06-22
申请人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号： H01L29/772 , H01L21/20 , H01L29/161
CPC分类号： H01L29/66795 , H01L29/1054 , H01L29/66484 , H01L29/785
摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
摘要翻译：多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。鳍状结构位于基板上。栅极结构设置在鳍状结构和衬底的一部分上。外延结构位于栅极结构旁边的鳍状结构上。梯度盖层位于每个外延结构上。梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从下到上减小的梯度分布。此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

17. 发明申请

US20130105912A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130105912A1
公开(公告)日：2013-05-02
申请号：US13283603
申请日：2011-10-28
申请人： Chun-Wei Hsu , Po-Cheng Huang , Ren-Peng Huang , Jie-Ning Yang , Chia-Lin Hsu , Teng-Chun Tsai , Chih-Hsun Lin , Chang-Hung Kung , Yen-Ming Chen , Yu-Ting Li
发明人： Chun-Wei Hsu , Po-Cheng Huang , Ren-Peng Huang , Jie-Ning Yang , Chia-Lin Hsu , Teng-Chun Tsai , Chih-Hsun Lin , Chang-Hung Kung , Yen-Ming Chen , Yu-Ting Li
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在电阻器区域的衬底上形成浅沟槽隔离（STI）; 在电阻区域的STI中形成槽; 并且在罐中形成电阻器，并且在与槽的两侧相邻的STI的表面上形成电阻器。

18. 发明申请

US20130052778A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20130052778A1
公开(公告)日：2013-02-28
申请号：US13216259
申请日：2011-08-24
申请人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
发明人： Chin-I Liao , Chia-Lin Hsu , Ming-Yen Li , Hsin-Huei Wu , Yung-Lun Hsieh , Chien-Hao Chen , Bo-Syuan Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66628
摘要： A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.
摘要翻译：半导体工艺包括以下步骤。提供基板。在基板上形成至少一个鳍状结构。在基板上形成氧化层，而不形成鳍状结构。形成栅极以覆盖氧化物层的一部分和鳍状结构的一部分。进行蚀刻处理以蚀刻栅极旁边的鳍状结构的一部分，因此在鳍状结构中至少形成凹部。执行外延工艺以在凹部中形成外延层，其中外延层具有六边形轮廓结构。

19. 发明申请

US20130015524A1 SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有金属门的半导体器件及其制造方法
公开(公告)号：US20130015524A1
公开(公告)日：2013-01-17
申请号：US13180556
申请日：2011-07-12
申请人： Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
发明人： Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/28008 , H01L21/28123 , H01L21/31053 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.
摘要翻译：具有金属栅极的半导体器件包括具有形成在其中的至少一个金属栅极的至少一个金属栅极和分别位于该金属的两侧的至少一对辅助虚拟结构的基板，其中形成有多个浅沟槽隔离物（STI）门和衬底上。

20. 发明授权

US07368042B2 Electroplating apparatus including a real-time feedback system 有权
标题翻译：电镀设备包括实时反馈系统
公开(公告)号：US07368042B2
公开(公告)日：2008-05-06
申请号：US10905361
申请日：2004-12-30
申请人： Chia-Lin Hsu , Kun-Hsien Lin , Wen-Chieh Su
发明人： Chia-Lin Hsu , Kun-Hsien Lin , Wen-Chieh Su
IPC分类号： B23H3/02
CPC分类号： C25D17/001 , C25D17/12 , C25D21/12
摘要： An electro-chemical plating system includes an upper rotor assembly for receiving and holding a wafer; an electroplating reactor vessel for containing plating solution in which the wafer is immersed; an anode array including a plurality of concentric anode segments provided inside the electroplating reactor vessel; a power supply system including power supply subunits for controlling electrical potentials of the anode segments, respectively; and a plurality of sensor devices mounted inside the upper rotor assembly, wherein the sensor devices are substantially arranged in corresponding to the anode segments, and during operation, the plurality of sensor devices are utilized for in-situ feeding back a deposition profile to a control unit in real time.
摘要翻译：电化学电镀系统包括用于接收和保持晶片的上转子组件; 电镀反应器容器，用于容纳浸有晶片的镀液; 阳极阵列，包括设置在所述电镀反应器容器内部的多个同心阳极段; 电源系统，包括分别用于控制阳极段的电位的电源子单元; 以及安装在上转子组件内部的多个传感器装置，其中传感器装置基本上布置成对应于阳极段，并且在操作期间，多个传感器装置用于将沉积轮廓原位反馈到控制器单位实时。

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