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11. 发明申请

US20110156102A1 MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20110156102A1
公开(公告)日：2011-06-30
申请号：US13045153
申请日：2011-03-10
申请人： CHUN-YUAN LO , Cheng-Ming Yih , Wen-Pin Lu
发明人： CHUN-YUAN LO , Cheng-Ming Yih , Wen-Pin Lu
IPC分类号： H01L23/52 , H01L21/8239
CPC分类号： H01L27/11519 , G11C5/005 , G11C5/025 , G11C5/063 , G11C8/14 , H01L27/11565
摘要： A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.
摘要翻译：提供包括多个存储单元，多个字线，虚拟字线，至少第一导电区域和至少第一插头的存储器阵列。每个字线耦合到相应的存储单元。虚拟字线与多个字线的最外侧字线直接相邻。第一导电区域仅设置在虚拟字线和最外侧字线之间。第一个插头位于虚拟字线和最外面的字线之间。

12. 发明申请

US20100323483A1 METHOD OF FABRICATING MEMORY 有权
标题翻译：制作记忆的方法
公开(公告)号：US20100323483A1
公开(公告)日：2010-12-23
申请号：US12851790
申请日：2010-08-06
申请人： Cheng-Ming Yih
发明人： Cheng-Ming Yih
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L29/7881 , H01L21/28247 , H01L21/28273 , H01L29/42324
摘要： A method of fabricating a semiconductor device is provided. First, a stacked structure is formed on a substrate. The stacked structure includes, from the substrate, a dielectric layer and a conductive gate in order. An ion implant process is performed to form doped regions in the substrate on the opposite sides of the stacked structure. Thereafter, source-side spacer is formed on a sidewall of the stacked structure. A thermal process is performed to activate the doped regions, thereby forming a source in the substrate under the sidewall of the stacked structure having the source-side spacer and a drain in the substrate on another side of the stacked structure.
摘要翻译：提供一种制造半导体器件的方法。首先，在基板上形成层叠结构。叠层结构依次包括介质层和导电栅极。执行离子注入工艺以在层叠结构的相对侧上的衬底中形成掺杂区域。此后，在层叠结构的侧壁上形成源极间隔物。执行热处理以激活掺杂区域，从而在层叠结构的侧壁的衬底内形成源，该层的结构具有源极侧隔离物和衬底中位于堆叠结构另一侧的漏极。

13. 发明授权

US07795665B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US07795665B2
公开(公告)日：2010-09-14
申请号：US11767192
申请日：2007-06-22
申请人： Cheng-Ming Yih
发明人： Cheng-Ming Yih
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L29/7881 , H01L21/28247 , H01L21/28273 , H01L29/42324
摘要： A flash memory comprising a substrate, a stacked structure over the substrate, a source, a drain and a source-side spacer is provided. The stacked structure includes a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The source and the drain are disposed in the substrate on the sides of the floating gate, respectively. The source-side spacer is disposed on a sidewall of the stacked structure near the source, thereby preventing the tunneling oxide layer and the inter-gate dielectric layer near the source from being re-oxidized, resulting in an increased thickness.
摘要翻译：提供了一种闪存，其包括衬底，在衬底上的堆叠结构，源极，漏极和源极间隔物。层叠结构包括隧道氧化物层，隧道氧化物层上的浮动栅极，浮置栅极上的栅极间介电层和栅极间电介质层上的控制栅极。源极和漏极分别设置在浮动栅极的侧面上的衬底中。源极间隔件设置在靠近源极的堆叠结构的侧壁上，从而防止源极附近的隧道氧化物层和栅极间电介质层被再次氧化，导致厚度增加。

14. 发明申请

US20090046516A1 DATA WRITING METHOD FOR FLASH MEMORIES 有权
标题翻译：闪存存储器的数据写入方法
公开(公告)号：US20090046516A1
公开(公告)日：2009-02-19
申请号：US11839255
申请日：2007-08-15
申请人： Chih-Hao Ho , Cheng-Ming Yih
发明人： Chih-Hao Ho , Cheng-Ming Yih
IPC分类号： G11C11/34
CPC分类号： G11C16/12
摘要： A data writing method for flash memories suitable for a flash memory using a switching unit to control a bit line thereof is disclosed. The data writing method for flash memories includes applying a square wave signal to a word line of the flash memory and applying a descent wave signal to the switching unit for the bit line of the flash memory to receive a fixed drain voltage.
摘要翻译：公开了一种适用于使用切换单元来控制其位线的闪存的闪速存储器的数据写入方法。用于闪速存储器的数据写入方法包括将方波信号施加到闪速存储器的字线，并将下降波信号施加到闪速存储器的位线的开关单元以接收固定的漏极电压。

15. 发明申请

US20100202179A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20100202179A1
公开(公告)日：2010-08-12
申请号：US12366910
申请日：2009-02-06
申请人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
发明人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
IPC分类号： G11C5/02 , G11C7/02
CPC分类号： H01L27/11519 , G11C5/005 , G11C5/025 , G11C5/063 , G11C8/14 , H01L27/11565
摘要： A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.
摘要翻译：提供存储器件。存储器件包括衬底，多个字线，多个导电区域和至少屏蔽插头。衬底具有存储区域和周边区域。字线设置在基板上，并且至少设置在周边区域中并与字线相邻的虚拟字线。导电区域分别设置在基板中和字线之间。屏蔽插头位于基板上并且与虚拟字线相邻，并且在虚拟字线和字线之间，并且在伪字线周围没有自对准源极区域。

16. 发明申请

US20080315287A1 FLASH MEMORY AND METHOD OF FABRICATING THE SAME 有权
标题翻译：闪存及其制作方法
公开(公告)号：US20080315287A1
公开(公告)日：2008-12-25
申请号：US11767192
申请日：2007-06-22
申请人： Cheng-Ming Yih
发明人： Cheng-Ming Yih
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28247 , H01L21/28273 , H01L29/42324
摘要： A flash memory comprising a substrate, a stacked structure over the substrate, a source, a drain and a source-side spacer is provided. The stacked structure includes a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The source and the drain are disposed in the substrate on the sides of the floating gate, respectively. The source-side spacer is disposed on a sidewall of the stacked structure near the source, thereby preventing the tunneling oxide layer and the inter-gate dielectric layer near the source from being re-oxidized, resulting in an increased thickness.
摘要翻译：提供了一种闪存，其包括衬底，在衬底上的堆叠结构，源极，漏极和源极间隔物。层叠结构包括隧道氧化物层，隧道氧化物层上的浮动栅极，浮置栅极上的栅极间介电层和栅极间电介质层上的控制栅极。源极和漏极分别设置在浮动栅极的侧面上的衬底中。源极间隔件设置在靠近源极的堆叠结构的侧壁上，从而防止源极附近的隧道氧化物层和栅极间电介质层被再次氧化，导致厚度增加。

17. 发明授权

US07319618B2 Low-k spacer structure for flash memory 有权
标题翻译：用于闪存的Low-k间隔结构
公开(公告)号：US07319618B2
公开(公告)日：2008-01-15
申请号：US11204537
申请日：2005-08-16
申请人： Chu-Ching Wu , Cheng-Ming Yih
发明人： Chu-Ching Wu , Cheng-Ming Yih
IPC分类号： G11C11/34
CPC分类号： H01L29/6656 , H01L21/28273 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.
摘要翻译：闪存单元包括具有主表面的硅衬底，位于主表面附近的硅衬底的一部分中的源极区域和位于主表面附近的硅衬底的一部分中的漏极区域。漏极区域与源极区域间隔开。所述存储单元包括形成在所述主表面上的第一介电层，设置在所述第一介电层上方的浮置栅极，设置在所述浮置栅极上方的栅极间电介质层，设置在所述栅极间电介质层上方的控制栅极，电介质层和设置在第二电介质层上的低k电介质间隔层。第一电介质层覆盖源极和漏极之间的主表面的一部分。第二电介质层围绕第一电介质层，控制栅极，栅极间电介质层和浮置栅极的外部部分。

18. 发明申请

US20070171712A1 Bitline transistor architecture for flash memory 有权
标题翻译：闪存的位线晶体管结构
公开(公告)号：US20070171712A1
公开(公告)日：2007-07-26
申请号：US11339092
申请日：2006-01-25
申请人： Chu-Ching Wu , Cheng-Ming Yih
发明人： Chu-Ching Wu , Cheng-Ming Yih
IPC分类号： G11C16/04 , G11C8/00 , G11C11/34
CPC分类号： H01L27/115 , H01L27/105
摘要： A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.
摘要翻译：存储器阵列包括掩埋扩散区域，向掩埋扩散区域提供电力的第一源极线，向掩埋扩散区域提供电能的第二源极线，具有第一沟道宽度的第一位线晶体管和第二位线晶体管具有第二通道宽度。第一位线晶体管靠近第一源极线并且电耦合到第一存储器单元。第一位线晶体管设置在第一和第二源极线之间。第二位线晶体管靠近第一位线晶体管并且电耦合到第二存储器单元。第二位线晶体管设置在第一和第二源极线之间，并且比第一位线晶体管更远离第一源极线。第二通道宽度大于第一通道宽度。

19. 发明申请

US20110062507A1 SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110062507A1
公开(公告)日：2011-03-17
申请号：US12559781
申请日：2009-09-15
申请人： Tin-Wei Wu , Cheng-Ming Yih , Chih-Hsiang Yang
发明人： Tin-Wei Wu , Cheng-Ming Yih , Chih-Hsiang Yang
IPC分类号： H01L29/788
CPC分类号： H01L21/823468 , H01L21/823418 , H01L27/11526 , H01L27/11546 , H01L29/66825
摘要： A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates.
摘要翻译：提供半导体器件。半导体器件包括存储器件，并且存储器件包括衬底，两个堆叠栅极，两个间隔物，绝缘层和介电层。其间具有间隙的层叠栅极位于基板上。在其间具有管或接缝的间隔件分别位于间隙中的每个堆叠栅极的侧壁处。管或接缝填充有绝缘层。电介质层位于衬底上并覆盖绝缘层和堆叠栅极。

20. 发明授权

US07846794B2 Low-K spacer structure for flash memory 有权
标题翻译：用于闪存的Low-K间隔结构
公开(公告)号：US07846794B2
公开(公告)日：2010-12-07
申请号：US11943888
申请日：2007-11-21
申请人： Chu-Ching Wu , Cheng-Ming Yih
发明人： Chu-Ching Wu , Cheng-Ming Yih
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/28273 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.
摘要翻译：闪存单元包括具有主表面的硅衬底，位于主表面附近的硅衬底的一部分中的源极区域和靠近主表面的硅衬底的一部分中的漏极区域。漏极区域与源极区域间隔开。所述存储单元包括形成在所述主表面上的第一介电层，设置在所述第一介电层上方的浮置栅极，设置在所述浮置栅极上方的栅极间电介质层，设置在所述栅极间电介质层上方的控制栅极，电介质层和设置在第二电介质层上的低k电介质间隔层。第一电介质层覆盖源极和漏极之间的主表面的一部分。第二电介质层围绕第一电介质层，控制栅极，栅极间电介质层和浮置栅极的外部部分。

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