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11. 发明授权

US08570068B2 Circuit for reducing negative bias temperature instability 有权
标题翻译：降低负偏压温度不稳定性的电路
公开(公告)号：US08570068B2
公开(公告)日：2013-10-29
申请号：US12768899
申请日：2010-04-28
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Ming-Chieh Huang , Bryan Sheffield , Chih-Chang Lin
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Ming-Chieh Huang , Bryan Sheffield , Chih-Chang Lin
IPC分类号： H03K19/0175
CPC分类号： H03K19/01855 , H03K3/012 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H03K19/0963
摘要： A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.
摘要翻译：电路包括逻辑门驱动器的操作PMOS晶体管。控制电路被配置为在待机模式期间关闭操作PMOS晶体管。电路还包括耦合到输出节点的牺牲PMOS晶体管。操作PMOS晶体管耦合到输出节点。牺牲PMOS晶体管被配置为在待机模式期间将输出节点保持在逻辑1。

12. 发明授权

US08217729B2 Integrated circuits including an LC tank circuit and operating methods thereof 有权
标题翻译：包括LC电路的集成电路及其操作方法
公开(公告)号：US08217729B2
公开(公告)日：2012-07-10
申请号：US12706825
申请日：2010-02-17
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Chiang Pu , Chih-Chang Lin
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Chiang Pu , Chih-Chang Lin
IPC分类号： H03B5/08
CPC分类号： H03L5/00 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03L7/099
摘要： An integrated circuit includes an inductor-capacitor (LC) tank circuit coupled with a feedback loop. The LC tank circuit is configured to output an output signal having a peak voltage that is substantially equal to a direct current (DC) voltage level plus an amplitude. The feedback loop is capable of determining if the peak voltage of the output signal falls within a range between a first voltage level and a second voltage level for adjusting the amplitude of the output signal.
摘要翻译：集成电路包括与反馈回路耦合的电感器 - 电容（LC）电路。 LC槽电路被配置为输出具有基本上等于直流（DC）电压电平加上幅度的峰值电压的输出信号。反馈回路能够确定输出信号的峰值电压是否落在用于调节输出信号的幅度的第一电压电平和第二电压电平之间的范围内。

13. 发明申请

US20110199063A1 INTEGRATED CIRCUITS INCLUDING AN LC TANK CIRCUIT AND OPERATING METHODS THEREOF 有权
标题翻译：集成电路，包括液相色谱电路及其操作方法
公开(公告)号：US20110199063A1
公开(公告)日：2011-08-18
申请号：US12706825
申请日：2010-02-17
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Chiang Pu , Chih-Chang Lin
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Chiang Pu , Chih-Chang Lin
IPC分类号： G05F1/10
CPC分类号： H03L5/00 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03L7/099
摘要： An integrated circuit includes an inductor-capacitor (LC) tank circuit coupled with a feedback loop. The LC tank circuit is configured to output an output signal having a peak voltage that is substantially equal to a direct current (DC) voltage level plus an amplitude. The feedback loop is capable of determining if the peak voltage of the output signal falls within a range between a first voltage level and a second voltage level for adjusting the amplitude of the output signal.
摘要翻译：集成电路包括与反馈回路耦合的电感器 - 电容（LC）电路。 LC槽电路被配置为输出具有基本上等于直流（DC）电压电平加上幅度的峰值电压的输出信号。反馈回路能够确定输出信号的峰值电压是否落在用于调节输出信号的幅度的第一电压电平和第二电压电平之间的范围内。

14. 发明授权

US08207775B2 VOL up-shifting level shifters 有权
标题翻译： VOL上移电平转换器
公开(公告)号：US08207775B2
公开(公告)日：2012-06-26
申请号：US12871343
申请日：2010-08-30
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Yuwen Swei , Chih-Chang Lin
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Yuwen Swei , Chih-Chang Lin
IPC分类号： H03L5/00
CPC分类号： H03K19/0941 , H03K3/356182 , H03K19/018514
摘要： A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.
摘要翻译：代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。第一和第二单向导流器件耦合到动态偏置电流源电路。电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。第一和第二下拉装置分别耦合到第一和第二单向导流装置。上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置电流源电路，第一下拉装置不导通，第二下拉装置导通。

15. 发明授权

US09524934B2 Integrated circuits with electrical fuses and methods of forming the same 有权
标题翻译：具有电熔丝的集成电路及其形成方法
公开(公告)号：US09524934B2
公开(公告)日：2016-12-20
申请号：US13302335
申请日：2011-11-22
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Kuoyuan (Peter) Hsu
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Kuoyuan (Peter) Hsu
IPC分类号： H01L21/8238 , H01L23/525 , H01L27/06 , H01L29/51 , H01L29/66
CPC分类号： H01L23/5256 , H01L21/823437 , H01L27/0617 , H01L27/0629 , H01L27/11206 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.
摘要翻译：形成集成电路的方法包括在衬底上形成至少一个晶体管。形成至少一个晶体管包括在衬底上形成栅极电介质结构。在栅介电结构上形成功函数金属层。在功函数金属层上形成导电层。源极/漏极（S / D）区域形成为与栅极电介质结构的每个侧壁相邻。在衬底上形成至少一个电熔丝。形成至少一个电熔丝包括在衬底上形成第一半导体层。在第一半导体层上形成第一硅化物层。

16. 发明授权

US08661389B2 Systems and methods of designing integrated circuits 有权
标题翻译：设计集成电路的系统和方法
公开(公告)号：US08661389B2
公开(公告)日：2014-02-25
申请号：US13084748
申请日：2011-04-12
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Li-Chun Tien
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of designing an integrated circuit includes providing a cell library including a first and second cell structures. The cell structures each include a dummy gate electrode disposed on a boundary. An edge gate electrode is disposed adjacent to the dummy gate electrode. An oxide definition (OD) region has an edge disposed between the edge gate electrode and the dummy gate electrode. The method includes determining if the cell structures are to be abutted with each other. If so, the method includes abutting the cell structures. If not so, the method includes increasing areas of portions of the OD regions between the edge gate electrodes and the dummy gate electrodes.
摘要翻译：设计集成电路的方法包括提供包括第一和第二单元结构的单元库。电池结构各自包括设置在边界上的虚拟栅电极。边缘栅电极被设置成与虚拟栅电极相邻。氧化物定义（OD）区域具有设置在边缘栅电极和伪栅电极之间的边缘。该方法包括确定单元结构是否彼此邻接。如果是，则该方法包括邻接单元结构。如果不是这样，则该方法包括增加边缘栅极电极和虚拟栅电极之间的OD区域的部分区域。

17. 发明授权

US08835246B2 Integrated circuits with resistors and methods of forming the same 有权
标题翻译：具有电阻器的集成电路及其形成方法
公开(公告)号：US08835246B2
公开(公告)日：2014-09-16
申请号：US13035533
申请日：2011-02-25
申请人： Chan-Hong Chern , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Fu-Lung Hsueh
IPC分类号： H01L27/088 , H01L27/06
CPC分类号： H01L27/0629 , H01L27/1207 , H01L28/20 , H01L29/42364 , H01L29/42372 , H01L29/4958 , H01L29/4966 , H01L29/4975
摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate.
摘要翻译：形成集成电路的方法包括在衬底上形成至少一个晶体管。所述至少一个晶体管包括设置在衬底上的第一栅极电介质结构。工作功能金属层设置在第一栅极电介质结构上。导电层设置在功函数金属层上。源极/漏极（S / D）区域邻近第一栅极电介质结构的每个侧壁设置。在衬底上形成至少一个电阻器结构。所述至少一个电阻器结构包括设置在所述衬底上的第一掺杂半导体层。至少一个电阻器结构不包括在第一掺杂半导体层和衬底之间的任何功函数金属层。

18. 发明授权

US08258602B2 Bipolar junction transistors having a fin 有权
标题翻译：具有翅片的双极结晶体管
公开(公告)号：US08258602B2
公开(公告)日：2012-09-04
申请号：US12618425
申请日：2009-11-13
申请人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
发明人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/73 , H01L21/823431
摘要： Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region.
摘要翻译：描述用于制造双极结型晶体管的设计和方法。在一个实施例中，半导体器件包括包括第一发射极区域，第一基极区域和第一集电极区域的第一鳍片。第一发射极区域，第一基极区域和第一集电极区域形成双极结型晶体管。第二翅片邻近并平行于第一翅片设置。第二鳍片包括与第一基底区域的第一接触。

19. 发明授权

US08957482B2 Electrical fuse and related applications 有权
标题翻译：电熔丝及相关应用
公开(公告)号：US08957482B2
公开(公告)日：2015-02-17
申请号：US12731325
申请日：2010-03-25
申请人： Fu-Lung Hsueh , Tao Wen Chung , Po-Yao Ke , Shine Chung
发明人： Fu-Lung Hsueh , Tao Wen Chung , Po-Yao Ke , Shine Chung
IPC分类号： H01L23/62 , H01L27/06 , H01L23/525 , H01L27/112 , H01L27/10 , H01L29/78
CPC分类号： H01L23/5256 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/785 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.
摘要翻译：在各种实施例中，熔丝由硅化物形成，并且在翅片结构的翅片的顶部上形成。因为熔丝形成在翅片的顶部，所以它的宽度取得了非常薄的翅片的宽度。根据实施方案，保险丝也使用平面技术形成并且包括薄的宽度。因为保险丝的宽度较薄，所以能够可靠地使保险丝断开。此外，熔丝可以与晶体管一起使用以形成用于存储器阵列的存储单元，并且晶体管利用FinFET技术。

20. 发明授权

US08305790B2 Electrical anti-fuse and related applications 有权
标题翻译：电抗保险丝及相关应用
公开(公告)号：US08305790B2
公开(公告)日：2012-11-06
申请号：US12724556
申请日：2010-03-16
申请人： Tao-Wen Chung , Po-Yao Ke , Shine Chung , Fu-Lung Hsueh
发明人： Tao-Wen Chung , Po-Yao Ke , Shine Chung , Fu-Lung Hsueh
IPC分类号： G11C17/00
CPC分类号： H01L23/5252 , G11C17/16 , H01L27/112 , H01L29/785 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A first terminal and a second terminal of a FinFET transistor are used as two terminals of an anti-fuse. To program the anti-fuse, a gate of the FinFET transistor is controlled, and a voltage having a predetermined amplitude and a predetermined duration is applied to the first terminal to cause the first terminal to be electrically shorted to the second terminal.
摘要翻译： FinFET晶体管的第一端子和第二端子用作反熔丝的两个端子。为了对反熔丝进行编程，控制FinFET晶体管的栅极，并且将具有预定幅度和预定持续时间的电压施加到第一端子，以使第一端子与第二端子电短路。

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