专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US09136366B2 Transistor with coupled gate and ground plane 有权
标题翻译：具有耦合栅极和接地层的晶体管
公开(公告)号：US09136366B2
公开(公告)日：2015-09-15
申请号：US14156559
申请日：2014-01-16
申请人： Commissariat a l'energie atomique et aux energies alternatives , STMicroelectronics SA
发明人： Bastien Giraud , Jean-Philippe Noel , Maud Vinet
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L29/772 , H01L29/786
CPC分类号： H01L29/78 , H01L29/42392 , H01L29/66575 , H01L29/785 , H01L29/7855 , H01L29/7856 , H01L29/78696
摘要： An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.
摘要翻译：集成电路包括硅衬底，衬底上方的接地平面，接地平面上方的掩埋绝缘体层，掩埋绝缘体层上方的硅层，并由掩埋绝缘体层与接地层分离，以及FDSOI晶体管。晶体管具有适于在硅层中形成的沟道，硅层中和/或硅层上的源极和漏极，以及覆盖沟道的上表面的栅极，并且具有覆盖沟道的侧面的侧面部分，以及在地面以上。横向部分和接地面之间的距离不大于接地平面和硅层之间的掩埋绝缘体层的厚度的三纳米至少五倍。接地层由掩埋绝缘体层与栅极分离。

12. 发明申请

US20140312461A1 DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET 有权
标题翻译：绝缘子MOSFET上的全绝缘硅的缺陷P-N结
公开(公告)号：US20140312461A1
公开(公告)日：2014-10-23
申请号：US13866077
申请日：2013-04-19
申请人： Commissariat A L'Energie Atomique Et Aux Energies Alternatives , INTERNATIONAL BUSINESS MACHINES CORPORATION , STMICROELECTRONICS, INC.
发明人： Kangguo Cheng , Bruce B. Doris , Laurent Grenouillet , Ali Khakifirooz , Yannick Le Tiec , Qing Liu , Maud Vinet
IPC分类号： H01L21/761 , H01L29/06
CPC分类号： H01L21/2253 , H01L21/761 , H01L21/7624 , H01L21/76243 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/0684 , H01L29/66477 , H01L29/66772 , H01L29/78612 , H01L29/78648
摘要： Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.
摘要翻译：用于半导体制造的方法包括在半导体衬底中形成阱。在阱内形成一个口袋，该口袋具有与阱相反的掺杂极性，以在阱和口袋之间提供p-n结。在p-n结处产生缺陷，使得p-n结的漏电阻减小。

13. 发明申请

US20130113066A1 UTBB CMOS IMAGER 有权
公开(公告)号：US20130113066A1
公开(公告)日：2013-05-09
申请号：US13661418
申请日：2012-10-26
申请人： Commissariat A L'Energie Atomique et Aux Energies Alternatives
发明人： Laurent GRENOUILLET , Maud Vinet
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/146 , H01L27/1461 , H01L27/14612 , H01L27/14632 , H01L27/14636 , H01L27/1464 , H01L27/14694 , H01L31/18
摘要： An image sensor device comprising at least one transistor lying on a semiconductor-on-insulator substrate, the substrate comprising a thin semi-conducting layer wherein a channel area of said transistor is made, an insulating layer separating the thin semi-conducting layer with a semi-conducting support layer, the device being characterized in that the semi-conducting support layer comprises at least one photosensitive area including at least one P-doped region and at least one N-doped region forming a junction provided facing the channel area of said transistor.
摘要翻译：一种图像传感器装置，包括位于绝缘体上半导体衬底上的至少一个晶体管，所述衬底包括薄半导电层，其中所述晶体管的沟道面积被制成，绝缘层将所述薄半导电层与该半导体支撑层的特征在于，半导体支撑层包括至少一个感光区域，该感光区域包括至少一个P掺杂区域和至少一个N掺杂区域，形成面向所述第一掺杂区域的沟道区域晶体管。

14. 发明授权

US11321626B2 Method for controlling a spin qubit quantum device 有权
公开(公告)号：US11321626B2
公开(公告)日：2022-05-03
申请号：US16626827
申请日：2018-06-27
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Leo Bourdet , Louis Hutin , Yann-Michel Niquet , Maud Vinet
IPC分类号： G06N10/00 , H01L29/10 , H01L29/66 , H01L29/76 , B82Y10/00
摘要： A method is described for controlling a spin qubit quantum device that includes a semiconducting portion, a dielectric layer covered by the semiconducting portion, a front gate partially covering an upper edge of the semiconducting portion, and a back gate. The method includes, during a manipulation of a spin state, the exposure of the device to a magnetic field B of value such that g·μB·B>min(Δ(Vbg)). The method also includes the application, on the rear gate, of an electrical potential Vbg of value such that Δ(Vbg)

15. 发明授权

US10679139B2 Quantum device comprising FET transistors and qubits co-integrated on the same substrate 有权
公开(公告)号：US10679139B2
公开(公告)日：2020-06-09
申请号：US16284103
申请日：2019-02-25
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Louis Hutin , Xavier Jehl , Maud Vinet
IPC分类号： H01L29/06 , H01L29/08 , H01L39/00 , G06N10/00 , H01L21/762 , H01L29/66 , H01L29/76 , H01L27/088 , H01L21/8234
摘要： Quantum device comprising: a quantum component forming a qubit, formed in an active layer of a substrate and comprising: a confinement region; charge carrier reservoirs; a first front gate covering the confinement region; first lateral spacers arranged around the first gate and covering access regions; an FET transistor formed in the active layer, comprising channel, source and drain regions formed in the active layer, a second front gate covering the channel region, and second lateral spacers arranged around the second front gate and covering source and drain extension regions; and wherein a width of the first lateral spacers is greater than that of the second lateral spacers.

16. 发明授权

US10651202B2 3D circuit transistors with flipped gate 有权
公开(公告)号：US10651202B2
公开(公告)日：2020-05-12
申请号：US16196390
申请日：2018-11-20
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Francois Andrieu , Perrine Batude , Maud Vinet
IPC分类号： H01L27/12 , H01L21/84 , H01L21/762 , H01L23/528 , H01L23/522 , H01L27/06 , H01L21/822 , H01L27/088 , H01L21/8234 , H01L23/532 , H01L21/033 , H01L21/768 , H01L21/285 , H01L21/8238 , H01L27/092
摘要： An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.

17. 发明申请

US20160211184A1 METHOD FOR MAKING A THREE DIMENSIONAL INTEGRATED ELECTRONIC CIRCUIT 有权
标题翻译：制造三维集成电子电路的方法
公开(公告)号：US20160211184A1
公开(公告)日：2016-07-21
申请号：US14993598
申请日：2016-01-12
申请人： Commissariat a l'energie atomique et aux energies alternatives
发明人： Bernard Previtali , Maud Vinet
IPC分类号： H01L21/84 , H01L21/8238 , H01L27/02 , H01L27/06
CPC分类号： H01L21/84 , H01L21/76895 , H01L21/8221 , H01L21/823871 , H01L23/485 , H01L23/5286 , H01L23/535 , H01L27/0251 , H01L27/0694
摘要： A method for making a three-dimensional integrated electronic circuit comprising steps for: making a first electrically conductive portion on a first dielectric layer covering a first semiconductor layer; then making a second dielectric layer covering the first electrically conductive portion such that the first electrically conductive portion is arranged between the first and second dielectric layers, and a second semiconductor layer arranged on the second dielectric layer; then making a first electronic component in the second semiconductor layer, and a second electronic component in the first semiconductor layer; then making an electrical interconnection electrically linking the first and second electronic components together, of which a first part passes through the first dielectric layer and electrically connects the second electronic component to the first electrically conductive portion and of which a second part passes through a part of the second dielectric layer and electrically connects the first electronic component to the first electrically conductive portion.
摘要翻译：一种制造三维集成电子电路的方法，包括以下步骤：在覆盖第一半导体层的第一介电层上制作第一导电部分; 然后制造覆盖第一导电部分的第二介电层，使得第一导电部分布置在第一和第二介电层之间，以及布置在第二介电层上的第二半导体层; 然后在第二半导体层中制造第一电子部件，在第一半导体层中制造第二电子部件; 然后制造将第一和第二电子部件电连接在一起的电互连，其中第一部分通过第一介电层并将第二电子部件电连接到第一导电部分，并且第二部分通过第第二电介质层并将第一电子部件电连接到第一导电部分。

18. 发明授权

US09293474B2 Dual channel hybrid semiconductor-on-insulator semiconductor devices 有权
公开(公告)号：US09293474B2
公开(公告)日：2016-03-22
申请号：US14739736
申请日：2015-06-15
申请人： International Business Machines Corporation , STMicroelectronics, Inc. , Commissariat A l'Energie atomique et aux Energies alternatives
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Qing Liu , Laurent Grenouillet , Yannick Le Tiec , Maud Vinet
IPC分类号： H01L27/12 , H01L21/762 , H01L21/84 , H01L29/06 , H01L29/16 , H01L29/161 , H01L21/02
CPC分类号： H01L27/1207 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/76224 , H01L21/76283 , H01L21/84 , H01L29/0649 , H01L29/1608 , H01L29/161
摘要： Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.

19. 发明申请

US20160035820A1 UNIAXIALLY-STRAINED FD-SOI FINFET 有权
公开(公告)号：US20160035820A1
公开(公告)日：2016-02-04
申请号：US14447678
申请日：2014-07-31
申请人： STMicroelectronics, Inc. , Commissariat a l'Energie Atomique et aux Energies Alternatives , GLOBALFOUNDRIES Inc.
发明人： Pierre Morin , Maud Vinet , Laurent Grenouillet , Ajey Poovannummoottil Jacob
IPC分类号： H01L29/06 , H01L29/78 , H01L29/66
CPC分类号： H01L29/0607 , H01L21/02636 , H01L21/283 , H01L21/3086 , H01L21/32 , H01L21/762 , H01L21/76264 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823481 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/0653 , H01L29/0665 , H01L29/1066 , H01L29/66477 , H01L29/66795 , H01L29/78 , H01L29/7847 , H01L29/7849
摘要： Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

20. 发明申请

US20150294904A1 METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS 有权
标题翻译：用于在有源区域部分地形成隔离斜面的微电子器件制造方法
公开(公告)号：US20150294904A1
公开(公告)日：2015-10-15
申请号：US14441354
申请日：2012-11-08
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Maud Vinet , Sylvie Mignot , Romain Wacquez
IPC分类号： H01L21/762 , H01L29/06 , H01L21/311
CPC分类号： H01L21/76283 , H01L21/311 , H01L21/76232 , H01L21/84 , H01L29/0649
摘要： A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.
摘要翻译：一种在包括第一半导体层，第一介电层和第二半导体层的衬底中制造微电子器件的方法，包括：通过第一半导体层，第一电介质层和第二半导体的一部分蚀刻沟槽层，限定一个有源区，并且使得在第二半导体层的水平处，沟槽的一部分在有源区的一部分下延伸; 在沟槽中沉积一个第二介电层; 蚀刻第二电介质层，使得第二电介质层的剩余部分形成在有源区的一部分下延伸的电介质材料的部分; 在沟槽中沉积第三电介质层，使得沟槽被第二和第三电介质层的电介质材料填充并形成隔离沟槽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式