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11. 发明申请

US20140170817A1 SILICON GERMANIUM AND GERMANIUM MULTIGATE AND NANOWIRE STRUCTURES FOR LOGIC AND MULTILEVEL MEMORY APPLICATIONS 审中-公开
标题翻译：硅锗和锗多晶硅和纳米结构用于逻辑和多种存储器应用
公开(公告)号：US20140170817A1
公开(公告)日：2014-06-19
申请号：US14184999
申请日：2014-02-20
申请人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L29/10 , H01L29/66 , H01L29/06
CPC分类号： H01L21/02381 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/31658 , H01L21/76283 , H01L21/823807 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/165 , H01L29/42324 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Sil-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Sil-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要翻译：一种提供晶体管或存储单元结构的方法。该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Sil-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Sil-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突出部。

12. 发明申请

US20090085027A1 THREE DIMENSIONAL STRAINED QUANTUM WELLS AND THREE DIMENSIONAL STRAINED SURFACE CHANNELS BY GE CONFINEMENT METHOD 有权
标题翻译：通过三维尺寸应变量子阱和三维应变表面通道
公开(公告)号：US20090085027A1
公开(公告)日：2009-04-02
申请号：US11864963
申请日：2007-09-29
申请人： Been-Yih Jin , Robert S. Chau , Brian S. Doyle , Jack T. Kavalieros
发明人： Been-Yih Jin , Robert S. Chau , Brian S. Doyle , Jack T. Kavalieros
IPC分类号： H01L29/12 , H01L21/205
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L29/0673 , H01L29/1054 , H01L29/66818 , H01L29/7851
摘要： The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开描述了通过Ge约束法实现3D（三维）应变高迁移量子阱结构和3D应变表面通道结构的方法和装置。一个示例性设备可以包括在Si衬底上的第一梯度SiGe鳍。第一级的SiGe鳍可以具有大于约60％的最大Ge浓度。 Ge量子阱可以在第一等级的SiGe鳍上，SiGe量子阱上阻挡层可以在Ge量子阱上。示例性设备还可以包括在Si衬底上的第二渐变SiGe鳍。第二级的SiGe鳍可以具有小于约40％的最大Ge浓度。 Si活性沟道层可以在第二级别的SiGe鳍上。可以使用诸如III-V族半导体的其它高迁移率材料作为活性通道材料。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

13. 发明申请

US20090170267A1 Tri-gate patterning using dual layer gate stack 有权
标题翻译：使用双层栅极堆叠的三栅极图案化
公开(公告)号：US20090170267A1
公开(公告)日：2009-07-02
申请号：US12006047
申请日：2007-12-28
申请人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
发明人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L21/336
CPC分类号： H01L21/823821 , H01L29/66795 , H01L29/785
摘要： In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A ploysilicon layer is formed over the silicon germanium layer and is polished. The ploysilicon layer over the first work function metal layer is thicker than the ploysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the ploysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.
摘要翻译：通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。在衬底上形成高介电常数层。在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。在第一和第二功函数金属层上形成硅锗层。在硅锗层上方形成硅层，并进行抛光。第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。硬掩模被图案化并用于蚀刻合金层和硅锗层以产生栅极堆叠。硅锗层的蚀刻速率比第一功函数金属层更快。

14. 发明申请

US20080237575A1 Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications 有权
标题翻译：用于逻辑和多级存储器应用的硅锗和锗多重和纳米线结构
公开(公告)号：US20080237575A1
公开(公告)日：2008-10-02
申请号：US11729565
申请日：2007-03-29
申请人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L29/15 , H01L21/335
CPC分类号： H01L21/02381 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/31658 , H01L21/76283 , H01L21/823807 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/165 , H01L29/42324 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要翻译：一种提供晶体管或存储单元结构的方法。该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。

15. 发明申请

US20110008937A1 SILICON GERMANIUM AND GERMANIUM MULTIGATE AND NANOWIRE STRUCTURES FOR LOGIC AND MULTILEVEL MEMORY APPLICATIONS 失效
标题翻译：硅锗和锗多晶硅和纳米结构用于逻辑和多种存储器应用
公开(公告)号：US20110008937A1
公开(公告)日：2011-01-13
申请号：US12885071
申请日：2010-09-17
申请人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/84
CPC分类号： H01L21/02381 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/31658 , H01L21/76283 , H01L21/823807 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/165 , H01L29/42324 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要翻译：一种提供晶体管或存储单元结构的方法。该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。

16. 发明申请

US20090001441A1 Three dimensional quantum dot array 审中-公开
标题翻译：三维量子点阵列
公开(公告)号：US20090001441A1
公开(公告)日：2009-01-01
申请号：US11823758
申请日：2007-06-28
申请人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/127 , B82Y10/00 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11517 , H01L29/40114 , H01L29/42332
摘要： In one embodiment of the invention, oxidation of silicon in a silicon germanium/silicon lattice may convert a two dimensional array of silicon germanium pillars into a structured three dimensional quantum dot array. The array may be included in, for example, flash memory floating gate, optical detector, or quantum computing device.
摘要翻译：在本发明的一个实施例中，硅锗/硅晶格中的硅的氧化可以将硅锗柱的二维阵列转换成结构化的三维量子点阵列。阵列可以包括在例如闪存浮动栅极，光学检测器或量子计算设备中。

17. 发明授权

US07821061B2 Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications 有权
标题翻译：用于逻辑和多级存储器应用的硅锗和锗多重和纳米线结构
公开(公告)号：US07821061B2
公开(公告)日：2010-10-26
申请号：US11729565
申请日：2007-03-29
申请人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/00
CPC分类号： H01L21/02381 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/31658 , H01L21/76283 , H01L21/823807 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/165 , H01L29/42324 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要翻译：一种提供晶体管或存储单元结构的方法。该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。

18. 发明授权

US07521775B2 Protection of three dimensional transistor structures during gate stack etch 有权
标题翻译：在栅堆叠蚀刻期间保护三维晶体管结构
公开(公告)号：US07521775B2
公开(公告)日：2009-04-21
申请号：US11452883
申请日：2006-06-13
申请人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
发明人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
IPC分类号： H01L29/06
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.
摘要翻译：本发明的实施例包括与具有高k电介质的三维晶体管和金属栅极相关的装置和方法，其翅片由其顶表面上的硬掩模层保护。在一个实施例中，硬掩模层包括氧化物。

19. 发明授权

US07485536B2 Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers 有权
标题翻译：通过原子层外延原位δ掺杂掺杂剂扩散阻挡层的突变结形成
公开(公告)号：US07485536B2
公开(公告)日：2009-02-03
申请号：US11326178
申请日：2005-12-30
申请人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
发明人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
IPC分类号： H01L21/335
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要： A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.
摘要翻译：一种方法，包括在衬底中的源区和漏区之间形成沟道区，所述沟道区包括第一掺杂物分布; 以及在所述沟道区和所述衬底的阱之间形成阻挡层，所述阻挡层包括不同于所述第一掺杂剂分布的第二掺杂剂分布。一种在基板上包括栅电极的装置; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及在衬底的阱和沟道区之间的阻挡层，阻挡层包括不同于沟道区的掺杂物分布并且不同于阱的掺杂剂分布的掺杂剂分布。一种包括包括微处理器的计算设备的系统，所述微处理器包括形成在衬底中的多个晶体管器件，所述多个晶体管器件中的每一个在所述衬底上包括栅电极; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及衬底的阱和沟道区之间的阻挡层。

20. 发明授权

US07714397B2 Tri-gate transistor device with stress incorporation layer and method of fabrication 有权
标题翻译：具有应力结合层的三栅晶体管器件及其制造方法
公开(公告)号：US07714397B2
公开(公告)日：2010-05-11
申请号：US11493789
申请日：2006-07-25
申请人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
发明人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/42384 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
摘要翻译：包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

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