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11. 发明授权

US5864341A Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding 失效
标题翻译：指令调度单元和方法，用于向不均匀转发的执行单元动态分类和发布指令
公开(公告)号：US5864341A
公开(公告)日：1999-01-26
申请号：US761875
申请日：1996-12-06
申请人： Troy Neal Hicks , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Troy Neal Hicks , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3891 , G06F9/3824 , G06F9/3853 , G06F9/3885
摘要： The present invention is directed to a method and apparatus for dispatching instructions in an information handling system. A pre-execution queue stores instructions, and at least one execution cluster is operably coupled to the pre-execution queue. An execution cluster comprises an early execution unit for executing a first instruction dispatched from the pre-execution queue to generate and forward a first result and a late execution unit for executing a second instruction dispatched from the pre-execution queue to generate and forward a second result after the first execution unit forwards the first result. The invention further includes circuitry operably associated with the pre-execution queue, and a method for prioritizing the order in which the instructions in the pre-execution queue are dispatched to the execution cluster.
摘要翻译：本发明涉及一种用于在信息处理系统中调度指令的方法和装置。预执行队列存储指令，并且至少一个执行群集可操作地耦合到预执行队列。执行群包括一个早期执行单元，用于执行从预执行队列发出的第一指令，以产生和转发第一结果;以及后期执行单元，用于执行从预执行队列发出的第二指令，以产生和转发第二个第一执行单元转发第一个结果后的结果。本发明还包括可操作地与预执行队列相关联的电路，以及用于将预执行队列中的指令分派到执行群集的顺序的优先级的方法。

12. 发明授权

US06266767B1 Apparatus and method for facilitating out-of-order execution of load instructions 有权
标题翻译：用于促进装载指令的无序执行的装置和方法
公开(公告)号：US06266767B1
公开(公告)日：2001-07-24
申请号：US09296871
申请日：1999-04-22
申请人： Kurt Alan Feiste , John Stephen Muhich , Steven Wayne White
发明人： Kurt Alan Feiste , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9312
CPC分类号： G06F9/3855 , G06F9/383 , G06F9/3834 , G06F9/3842
摘要： A processor (100) includes a preload queue (160) for storing a plurality of preload entries. Each preload entry is associated with a preload instruction and includes the address and byte count defined by the respective preload and an identifier associated with the respective preload. A comparison unit (170) associated with the preload queue (160) identifies each conflicting preload entry, that is, each preload entry associated with a preload instruction that conflicts with an older store instruction. The oldest preload instruction associated with one of the conflicting preload entries represents a target preload. The processor (100) may flush this target preload along with all instructions executed after the target preload in order to correct for the conflict between the target preload and store instruction.
摘要翻译：处理器（100）包括用于存储多个预加载条目的预加载队列（160）。每个预加载条目与预加载指令相关联，并且包括由相应的预载荷定义的地址和字节计数以及与相应的预载荷相关联的标识符。与预加载队列（160）相关联的比较单元（170）识别每个冲突的预加载条目，即与与旧存储指令冲突的预加载指令相关联的每个预加载条目。与其中一个冲突的预加载条目相关联的最早的预加载指令表示目标预加载。处理器（100）可以与目标预加载之后执行的所有指令一起刷新该目标预载荷，以便校正目标预加载和存储指令之间的冲突。

13. 发明授权

US6098167A Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution 失效
标题翻译：支持无序执行的处理器的快速统一中断恢复和分支恢复的装置和方法
公开(公告)号：US6098167A
公开(公告)日：2000-08-01
申请号：US829667
申请日：1997-03-31
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3863
摘要： In maintaining the state of a processor, a dispatched instruction is given an identification tag and an associated entry in an architectural register table. The identification tag of the dispatched instruction is written to the entry in the architectural register table, if the identification tag of the dispatched instruction is more recent than a prior instruction identification tag stored in the entry.
摘要翻译：在维护处理器的状态时，在架构寄存器表中给出分派指令的识别标签和相关联的条目。如果调度指令的识别标签比存储在条目中的先前指令标识标签更新，则将调度指令的识别标签写入架构寄存器表中的条目。

14. 发明授权

US6070238A Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction 失效
标题翻译：用于检测存储指令与先前执行的存储参考指令之间的重叠条件的方法和装置
公开(公告)号：US6070238A
公开(公告)日：2000-05-30
申请号：US927889
申请日：1997-09-11
申请人： Kurt Alan Feiste , John Stephen Muhich , Steven Wayne White
发明人： Kurt Alan Feiste , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/312 , G06F9/38 , G06F11/28
CPC分类号： G06F9/30043 , G06F11/28 , G06F9/3816 , G06F9/3834
摘要： One aspect of the invention relates to a super scalar processor having a memory which as addressable with respect to the combination of a page address and a page offset address, and provides a method for detecting an overlap condition between a present instruction and a previously executed instruction, the previously executed instruction being executed prior to execution of the present instruction. In one embodiment, the method comprises the steps of dividing the present instruction into a plurality of aligned memory accesses; determining the page offset for at least one of the aligned accesses; and comparing the page offset and byte count for the present instruction to a page offset and byte count for the previously executed instruction.
摘要翻译：本发明的一个方面涉及一种具有存储器的超标量处理器，该存储器相对于页地址和页偏移地址的组合可寻址，并且提供了一种用于检测当前指令和先前执行的指令之间的重叠条件的方法，在执行本指令之前执行的先前执行的指令。在一个实施例中，该方法包括以下步骤：将本指令划分成多个对齐的存储器存取; 确定对齐的访问中的至少一个的页偏移; 并将本指令的页偏移量和字节计数与先前执行的指令的页偏移量和字节数进行比较。

15. 发明授权

US5913048A Dispatching instructions in a processor supporting out-of-order execution 失效
标题翻译：支持无序执行的处理器中的调度指令
公开(公告)号：US5913048A
公开(公告)日：1999-06-15
申请号：US829663
申请日：1997-03-31
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of assigning an identification tag to an instruction, and dispatching the instruction, the identification tag and source information to an execution queue.
摘要翻译：本发明涉及一种在处理器中发出指令的方法。在本发明的一个版本中，该方法包括以下步骤：向指令分配识别标签，并将指令，识别标签和源信息分派到执行队列。

16. 发明授权

US5887161A Issuing instructions in a processor supporting out-of-order execution 失效
标题翻译：在支持无序执行的处理器中发出指令
公开(公告)号：US5887161A
公开(公告)日：1999-03-23
申请号：US829662
申请日：1997-03-31
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of dispatching the instruction and source information to a queue, determining validity of the source information, and issuing the instruction for execution in response to the source information validity.
摘要翻译：本发明涉及一种在处理器中发出指令的方法。在本发明的一个版本中，该方法包括以下步骤：将指令和源信息发送到队列，确定源信息的有效性，以及响应源信息有效性发出执行指令。

17. 发明授权

US5870612A Method and apparatus for condensed history buffer 失效
标题翻译：精简历史缓冲区的方法和装置
公开(公告)号：US5870612A
公开(公告)日：1999-02-09
申请号：US729309
申请日：1996-10-15
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/462 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： The invention includes a method and apparatus for maintaining content of predefined registers of a processor which uses the registers for executing instructions, including an interruptible instruction. According to the invention, instructions are dispatched, including instructions ("targeting instructions") which target registers for holding register content, and an interruptible instruction. The content of a register is altered in response to executing a targeting instruction. An entry of register content is stored only for selected ones of the dispatched targeting instructions.
摘要翻译：本发明包括一种用于维护处理器的预定义寄存器的内容的方法和装置，其使用该寄存器来执行包括可中断指令的指令。根据本发明，调度指令，包括目标用于保持寄存器内容的寄存器的指令（“目标指令”）和可中断指令。响应于执行目标指令而改变寄存器的内容。注册内容的条目仅存储于所选派生的定位指令。

18. 发明授权

US08037034B2 Methods of creating a dictionary for data compression 有权
标题翻译：创建数据压缩字典的方法
公开(公告)号：US08037034B2
公开(公告)日：2011-10-11
申请号：US11781833
申请日：2007-07-23
申请人： Piotr M. Plachta , Wolfram Sauer , Balakrishna Raghavendra Iyer , Steven Wayne White
发明人： Piotr M. Plachta , Wolfram Sauer , Balakrishna Raghavendra Iyer , Steven Wayne White
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： H03M7/3088
摘要： Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favors longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.
摘要翻译：本发明的一些方面提供用于创建静态词典的方法，系统和计算机程序产品，其中优选较长的字节串。为此，根据本发明的方面，定义新的启发式来代替用于记录数据树中的特定节点被访问次数的上述频率计数度量。新的启发式是基于对特定字节串的端节点进行访问的次数进行计数，而不会在每次访问这些节点时频繁地在字节串中间存储字符的节点递增计数。结果是有利于较长字节串的发生计数度量，偏向于不增加在字节串中间存储字符的节点的相应出现计数值。

19. 发明申请

US20100287339A1 DEMAND BASED PARTITIONING OR MICROPROCESSOR CACHES 失效
标题翻译：基于需求的分区或微处理器缓存
公开(公告)号：US20100287339A1
公开(公告)日：2010-11-11
申请号：US12437624
申请日：2009-05-08
申请人： Bret Ronald Olszewski , Steven Wayne White
发明人： Bret Ronald Olszewski , Steven Wayne White
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/127 , G06F12/084 , G06F12/0842
摘要： Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.
摘要翻译：通过将多个唯一的逻辑处理分区标识符接收到多核处理器的注册来管理和控制多核处理器高速缓冲存储器与逻辑分区的关联性，每个标识符与一个或多个核上的逻辑处理分区相关联的多核处理器; 响应于共享的高速缓存存储器未命中，识别高速缓存目录中与所述地址相关联的数据的位置，所述共享高速缓存存储器是多路组合的; 将新的高速缓存行条目与数据和所注册的唯一逻辑处理分区标识符之一相关联; 修改缓存目录以反映关联; 以及在所述新的高速缓存行条目处高速缓存所述数据，其中所述共享高速缓冲存储器在所述多核处理器的所述多个逻辑处理分区之间逐行地有效地共享。

20. 发明授权

US08458401B2 Demand based partitioning of microprocessor caches 失效
标题翻译：微处理器缓存的基于需求的划分
公开(公告)号：US08458401B2
公开(公告)日：2013-06-04
申请号：US13398443
申请日：2012-02-16
申请人： Bret Ronald Olszewski , Steven Wayne White
发明人： Bret Ronald Olszewski , Steven Wayne White
IPC分类号： G06F12/08
CPC分类号： G06F12/127 , G06F12/084 , G06F12/0842
摘要： Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein the shared cache memory is effectively shared on a line-by-line basis among the plurality of logical processing partitions of the multi-core processor.
摘要翻译：通过将多个唯一的逻辑处理分区标识符接收到多核处理器的注册来管理和控制多核处理器高速缓冲存储器与逻辑分区的关联性，每个标识符与一个或多个核上的逻辑处理分区相关联的多核处理器; 响应于共享的高速缓存存储器未命中，识别高速缓存目录中与所述地址相关联的数据的位置，所述共享高速缓存存储器是多路组合的; 将新的高速缓存行条目与数据和所注册的唯一逻辑处理分区标识符之一相关联; 修改缓存目录以反映关联; 以及将所述数据缓存在所述新的高速缓存行条目上，其中所述共享高速缓冲存储器在所述多核处理器的所述多个逻辑处理分区之间逐行地有效地共享。

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