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11. 发明申请

US20090174458A1 Level Shifter with Embedded Logic and Low Minimum Voltage 有权
标题翻译：具有嵌入式逻辑和低最小电压的电平变换器
公开(公告)号：US20090174458A1
公开(公告)日：2009-07-09
申请号：US12404597
申请日：2009-03-16
申请人： Brian J. Campbell , Vincent R. von Kaenel , Naveen Javarappa , Greg M. Hess
发明人： Brian J. Campbell , Vincent R. von Kaenel , Naveen Javarappa , Greg M. Hess
IPC分类号： H03L5/00
CPC分类号： H03K3/012 , H03K3/35613
摘要： In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.
摘要翻译：在一个实施例中，电平移位器电路可以包括移位级，其还将实现逻辑运算的晶体管嵌入到电平移位器的两个或更多个输入上。输入中的至少一个可以来自由与接收电平移位器输出的电平移位器和电路不同的电源供电的电路。此外，电平移位器包括一个或多个匹配执行逻辑运算的晶体管的虚拟晶体管，以改善电平移位器电路的对称性。在一些实施例中，某些设计和布局规则可以应用于电平移位器电路以限制在各种制造变化中的对称性的变化。

12. 发明授权

US08476930B2 Level shifter with embedded logic and low minimum voltage 有权
标题翻译：电平移位器具有嵌入式逻辑和低最小电压
公开(公告)号：US08476930B2
公开(公告)日：2013-07-02
申请号：US13171781
申请日：2011-06-29
申请人： Brian J. Campbell , Vincent R. von Kaenel , Naveen Javarappa , Greg M. Hess
发明人： Brian J. Campbell , Vincent R. von Kaenel , Naveen Javarappa , Greg M. Hess
IPC分类号： H03K19/094
CPC分类号： H03K3/012 , H03K3/35613
摘要： In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.
摘要翻译：在一个实施例中，电平移位器电路可以包括移位级，其还将实现逻辑运算的晶体管嵌入到电平移位器的两个或更多个输入上。输入中的至少一个可以来自由与接收电平移位器输出的电平移位器和电路不同的电源供电的电路。此外，电平移位器包括一个或多个匹配执行逻辑运算的晶体管的虚拟晶体管，以改善电平移位器电路的对称性。在一些实施例中，某些设计和布局规则可以应用于电平移位器电路以限制在各种制造变化中的对称性的变化。

13. 发明申请

US20120314516A1 Performing Stuck-At Testing Using Multiple Isolation Circuits 失效
标题翻译：使用多重隔离电路进行测试
公开(公告)号：US20120314516A1
公开(公告)日：2012-12-13
申请号：US13157433
申请日：2011-06-10
申请人： Brian J. Campbell , Daniel C. Murray , Conrad H. Ziesler
发明人： Brian J. Campbell , Daniel C. Murray , Conrad H. Ziesler
IPC分类号： G11C7/00
CPC分类号： G11C29/04 , G11C8/08 , G11C29/30 , G11C2029/1202
摘要： A memory may include a memory array, a plurality of control circuits, and a plurality of isolation circuits. The plurality of control circuits may be configured to generate control signals for the memory array. For example, the plurality of control circuits may include a plurality of word line driver circuits. The plurality of isolation circuits may be configured to receive the control signals from the plurality of control circuits and a plurality of isolation signals. A first isolation signal may correspond to the plurality of word line driver circuits and at least one second isolation signal may correspond to other ones of the plurality of control circuits. The first isolation signal and the second isolation signal may be independently controlled during memory tests to detect stuck-at faults associated with the plurality of isolation signals.
摘要翻译：存储器可以包括存储器阵列，多个控制电路和多个隔离电路。多个控制电路可以被配置为产生用于存储器阵列的控制信号。例如，多个控制电路可以包括多个字线驱动电路。多个隔离电路可以被配置为从多个控制电路接收控制信号和多个隔离信号。第一隔离信号可以对应于多个字线驱动器电路，并且至少一个第二隔离信号可以对应于多个控制电路中的其它控制电路。可以在存储器测试期间独立地控制第一隔离信号和第二隔离信号，以检测与多个隔离信号相关联的卡入故障。

14. 发明授权

US08203898B2 Leakage and NBTI reduction technique for memory 有权
标题翻译：记忆泄漏和NBTI降低技术
公开(公告)号：US08203898B2
公开(公告)日：2012-06-19
申请号：US13171748
申请日：2011-06-29
申请人： Brian J. Campbell , Greg M. Hess , Hang Huang
发明人： Brian J. Campbell , Greg M. Hess , Hang Huang
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C7/12 , G11C7/22 , G11C7/222 , G11C7/225
摘要： In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.
摘要翻译：在一个实施例中，集成电路包括逻辑电路和包括多个位线和位线预充电电路的存储器电路。存储器电路可以包括用于由逻辑电路输入产生的控制信号的电平移位器，特别地，可以有一个或多个电平移位器产生预充电使能信号以控制位线预充电电路。用于位线预充电电路的电平移位器也可以通过输入控制信号（这里为FloatBL）在存储器电路空闲的时间段期间被控制。如果FloatBL信号有效，则可能禁止位线预充电电路浮动位线。在一些实施例中，FloatBL信号还可以禁止位线上的位线位线保持电路。在一些实施例中，当存储器电路退出空闲状态时，位线预充电电路可以以交错方式启用。

15. 发明申请

US20100329062A1 Leakage and NBTI Reduction Technique for Memory 有权
标题翻译：记忆泄漏和NBTI减少技术
公开(公告)号：US20100329062A1
公开(公告)日：2010-12-30
申请号：US12492364
申请日：2009-06-26
申请人： Brian J. Campbell , Greg M. Hess , Hang Huang
发明人： Brian J. Campbell , Greg M. Hess , Hang Huang
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C7/04 , G11C7/12 , G11C7/22 , G11C7/222 , G11C7/225
摘要： In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.
摘要翻译：在一个实施例中，集成电路包括逻辑电路和包括多个位线和位线预充电电路的存储器电路。存储电路可以包括用于由逻辑电路输入产生的控制信号的电平移位器，特别地，可以有一个或多个电平移位器产生预充电使能信号以控制位线预充电电路。用于位线预充电电路的电平移位器也可以通过输入控制信号（这里为FloatBL）在存储器电路空闲的时间段期间被控制。如果FloatBL信号有效，则可能禁止位线预充电电路浮动位线。在一些实施例中，FloatBL信号还可以禁止位线上的位线位线保持电路。在一些实施例中，当存储器电路退出空闲状态时，位线预充电电路可以以交错方式启用。

16. 发明申请

US20100238745A1 Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage 有权
标题翻译：具有与逻辑电路电源电压不同的存储器的独立电源电压的集成电路
公开(公告)号：US20100238745A1
公开(公告)日：2010-09-23
申请号：US12791080
申请日：2010-06-01
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

17. 发明申请

US20100235670A1 Fast L1 Flush Mechanism 有权
标题翻译：快速L1冲洗机构
公开(公告)号：US20100235670A1
公开(公告)日：2010-09-16
申请号：US12785842
申请日：2010-05-24
申请人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
发明人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.
摘要翻译：在一个实施例中，处理器包括被配置为存储多个高速缓存块的数据高速缓存和耦合到数据高速缓存的控制单元。控制单元被配置为响应于处理器将转换到其中禁止用于处理器的一个或多个时钟的低功率状态的指示，从数据高速缓冲存储器中刷新多个高速缓存块。

18. 发明申请

US20100085079A1 Low Latency, Power-Down Safe Level Shifter 有权
标题翻译：低延迟，掉电安全电平移位器
公开(公告)号：US20100085079A1
公开(公告)日：2010-04-08
申请号：US12634791
申请日：2009-12-10
申请人： Brian J. Campbell , Vincent R. von Kaenel
发明人： Brian J. Campbell , Vincent R. von Kaenel
IPC分类号： H03K19/094
CPC分类号： H03K3/35613 , G11C5/14 , H03K3/012
摘要： In one embodiment, an apparatus comprises a circuit supplied by a first supply voltage during use, the circuit having at least a first input signal; and a level shifter supplied by the first supply voltage during use and coupled to provide the first input signal to the circuit. The level shifter is coupled to receive a second input signal sourced from circuitry supplied by a second supply voltage during use, and is configured to generate the first input signal by level shifting the second input signal. Coupled to receive a power control signal indicating, when asserted, that the second supply voltage is to be powered down, the level shifter is configured to assert a predetermined level on the first input signal independent of the second input signal and responsive to an assertion of the power control signal.
摘要翻译：在一个实施例中，一种装置包括在使用期间由第一电源电压提供的电路，该电路至少具有第一输入信号; 以及在使用期间由第一电源电压提供的电平移位器，并被耦合以向该电路提供第一输入信号。电平移位器被耦合以接收来自在使用期间由第二电源电压提供的电路的第二输入信号，并且被配置为通过电平移位第二输入信号来产生第一输入信号。耦合以接收功率控制信号，该信号指示当断言第二电源电压要断电时，电平移位器被配置为独立于第二输入信号来声明第一输入信号上的预定电平，并且响应于断言功率控制信号。

19. 发明授权

US07218562B2 Recovering bit lines in a memory array after stopped clock operation 有权
公开(公告)号：US07218562B2
公开(公告)日：2007-05-15
申请号：US11173119
申请日：2005-07-01
申请人： Brian J. Campbell
发明人： Brian J. Campbell
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C7/12 , G11C11/413
摘要： In one embodiment, an apparatus comprises a plurality of memory cells; first and second bit lines coupled to the plurality of memory cells; a first and second bit line precharge circuits coupled to the first and second bit lines; and a control circuit coupled to the first and second bit line precharge circuits. The first and second bit line precharge circuits are each configured to precharge the first bit line and the second bit line. The control circuit is coupled to receive an indication that one or more clocks are being restarted after a period of stopped clock operation, and is configured to activate both the first and second bit line precharge circuits responsive to the indication and independent of an operation to the memory that was interrupted by the period of stopped clock operation, if any.

20. 发明授权

US06989691B2 Dynamic to static converter with noise suppression 失效
标题翻译：具有噪声抑制的动态到静态转换器
公开(公告)号：US06989691B2
公开(公告)日：2006-01-24
申请号：US10748639
申请日：2003-12-30
申请人： Brian J. Campbell
发明人： Brian J. Campbell
IPC分类号： H03K19/096
CPC分类号： H03K3/356173 , H03K19/01855
摘要： An apparatus is disclosed which includes a converter circuit and a noise suppression circuit. The converter circuit has a dynamic logic input, and is configured to generate a static logic output on an output node responsive to the dynamic logic input. The noise suppression circuit is coupled to receive a clock signal and is coupled to the output node. Responsive to a first phase of the clock signal, a precharge of a dynamic logic circuit generating the dynamic logic input occurs. The noise suppression circuit is configured to actively drive the static logic output on the output node responsive to the first phase. In some embodiments, the noise suppression circuit may reduce the noise sensitivity of the static logic output during the precharge phase, and may not impede operation of the converter circuit during the evaluate phase.
摘要翻译：公开了一种包括转换器电路和噪声抑制电路的装置。转换器电路具有动态逻辑输入，并且被配置为响应于动态逻辑输入在输出节点上产生静态逻辑输出。噪声抑制电路被耦合以接收时钟信号并耦合到输出节点。响应于时钟信号的第一相位，发生产生动态逻辑输入的动态逻辑电路的预充电。噪声抑制电路被配置为响应于第一阶段主动地驱动输出节点上的静态逻辑输出。在一些实施例中，噪声抑制电路可以降低在预充电阶段期间静态逻辑输出的噪声灵敏度，并且可能不妨碍在评估阶段期间转换器电路的操作。

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