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11. 发明申请

US20060064518A1 Method and system for managing cache injection in a multiprocessor system 有权
标题翻译：在多处理器系统中管理缓存注入的方法和系统
公开(公告)号：US20060064518A1
公开(公告)日：2006-03-23
申请号：US10948407
申请日：2004-09-23
申请人： Patrick Bohrer , Ahmed Gheith , Peter Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
发明人： Patrick Bohrer , Ahmed Gheith , Peter Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.
摘要翻译：用于管理多处理器系统中的高速缓存注入的方法和装置减少与对称多处理器（SMP）或非均匀存储器访问（NUMA）多处理器环境中的直接存储器访问传输相关联的处理时间。该方法和装置可以检测目标处理器用于DMA完成或直接处理DMA完成到特定处理器，从而使高速缓存注入与执行DMA完成例程的处理器处理注入高速缓存的数据的处理器相连的高速缓存。可以通过确定处理器处理在DMA传输完成时发生的中断来识别目标处理器。或者或与目标处理器识别结合，中断处理程序可以将延迟过程调用排队到目标处理器以处理传送的数据。在NUMA多处理器系统中，选择完成的处理器/目标存储器，以便可访问目标存储器到处理器和相关联的高速缓存。

12. 发明授权

US08255591B2 Method and system for managing cache injection in a multiprocessor system 有权
标题翻译：在多处理器系统中管理缓存注入的方法和系统
公开(公告)号：US08255591B2
公开(公告)日：2012-08-28
申请号：US10948407
申请日：2004-09-23
申请人： Patrick Joseph Bohrer , Ahmed Gheith , Peter Heiner Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
发明人： Patrick Joseph Bohrer , Ahmed Gheith , Peter Heiner Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.
摘要翻译：用于管理多处理器系统中的高速缓存注入的方法和装置减少与对称多处理器（SMP）或非均匀存储器访问（NUMA）多处理器环境中的直接存储器访问传输相关联的处理时间。该方法和装置可以检测目标处理器用于DMA完成或直接处理DMA完成到特定处理器，从而使高速缓存注入与执行DMA完成例程的处理器处理注入高速缓存的数据的处理器相连的高速缓存。可以通过确定处理器处理在DMA传输完成时发生的中断来识别目标处理器。或者或与目标处理器识别结合，中断处理程序可以将延迟过程调用排队到目标处理器以处理传送的数据。在NUMA多处理器系统中，选择完成的处理器/目标存储器，以便可访问目标存储器到处理器和相关联的高速缓存。

13. 发明授权

US08966219B2 Address translation through an intermediate address space 有权
标题翻译：通过中间地址空间进行地址转换
公开(公告)号：US08966219B2
公开(公告)日：2015-02-24
申请号：US11928125
申请日：2007-10-30
申请人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/10
CPC分类号： G06F12/1063 , G06F12/1072
摘要： In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.
摘要翻译：在能够同时执行多个硬件执行线程的数据处理系统中，处理单元中的中间地址转换单元将存储器访问的有效地址转换为中间地址。使用中间地址访问高速缓冲存储器。响应于高速缓冲存储器中的缺失，中间地址被实现地址转换单元转换成实地址，该单元执行多个硬件执行线程的地址转换。使用实际地址访问系统内存。

14. 发明授权

US08843705B2 Read and write aware cache with a read portion and a write portion of a tag and status array 有权
标题翻译：具有读取部分和标签和状态数组的写入部分的读写感知高速缓存
公开(公告)号：US08843705B2
公开(公告)日：2014-09-23
申请号：US13572916
申请日：2012-08-13
申请人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F2212/271 , Y02D10/13
摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.
摘要翻译：在缓存中提供了一种机制，用于提供读写感知高速缓存。该机制将大型缓存分区分为常读区域和经常写区域。该机制将读/写频率视为非均匀缓存架构替换策略。经常写入的高速缓存行放置在更远的存储区之一中。经常读取的高速缓存行被放置在其中一个较近的存储体中。常读区域和经常写区域之间的大小比可以是静态的或动态的。经常读区域和经常写区域之间的边界可能是不同的或模糊的。

15. 发明申请

US20120266180A1 Performing Setup Operations for Receiving Different Amounts of Data While Processors are Performing Message Passing Interface Tasks 审中-公开
标题翻译：在处理器执行消息传递接口任务时，执行接收不同数据量的设置操作
公开(公告)号：US20120266180A1
公开(公告)日：2012-10-18
申请号：US13524585
申请日：2012-06-15
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/52 , G06F15/173
CPC分类号： G06F9/522 , G06F9/5083
摘要： A system and method are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.
摘要翻译：提供了一种系统和方法，用于在处理器执行消息传递接口（MPI）任务时执行用于接收不同数量的数据的建立操作。提供了用于调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 MPI负载平衡控制器维护一个历史记录，提供关于其对同步操作的调用的任务简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。结果，可以在处理器正在执行MPI任务以准备在基于历史的后续计算周期中接收不同大小的数据部分时执行设置操作。

16. 发明申请

US20120195591A1 DUAL NETWORK TYPES SOLUTION FOR COMPUTER INTERCONNECTS 有权
标题翻译：双网络类型计算机互连解决方案
公开(公告)号：US20120195591A1
公开(公告)日：2012-08-02
申请号：US13444762
申请日：2012-04-11
申请人： Alan Benner , Ramakrishnan Rajamony , Eugen Schenfeld , Craig Brian Stunkel , Peter A. Walker
发明人： Alan Benner , Ramakrishnan Rajamony , Eugen Schenfeld , Craig Brian Stunkel , Peter A. Walker
IPC分类号： H04L12/66 , H04J14/00
CPC分类号： H04L12/4641 , H04L12/28 , H04L12/66
摘要： A computing system includes: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously.
摘要翻译：计算系统包括：多个紧密耦合的处理节点; 使用电路交换模式的多个电路交换网络，互连处理节点，以及处理满足一个或多个标准的数据传输; 以及多个电子分组交换网络，其还互连处理节点，处理满足至少一个准则的数据传输。电路交换网络和电子分组交换网络同时工作。

17. 发明授权

US08146094B2 Guaranteeing delivery of multi-packet GSM messages 失效
标题翻译：保证多分组GSM消息的传送
公开(公告)号：US08146094B2
公开(公告)日：2012-03-27
申请号：US12024678
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F13/00 , G06F9/46 , G06F15/16 , H04J1/16 , H04B7/005 , H04B1/44
CPC分类号： H04L1/1642 , G06F9/542
摘要： A target task ensures complete delivery of a global shared memory (GSM) message from an originating task to the target task. The target task's HFI receives a first of multiple GSM packets generated from a single GSM message sent from the originating task. The HFI logic assigns a sequence number and corresponding tuple to track receipt of the complete GSM message. The sequence number is unique relative to other sequence numbers assigned to GSM messages that have not been completely received from the initiating task. The HFI updates a count value within the tuple, which comprises the sequence number and the count value for the first GSM packet and for each subsequent GSM packet received for the GSM message. The HFI determines when receipt of the GSM message is complete by comparing the count value with a count total retrieved from the packet header.
摘要翻译：目标任务确保从始发任务到目标任务的全局共享存储器（GSM）消息的完全传递。目标任务的HFI接收从发起任务发送的单个GSM消息产生的多个GSM分组中的第一个。 HFI逻辑分配序列号和对应的元组来跟踪完整GSM消息的接收。相对于分配给尚未完全从发起任务接收的GSM消息的其他序列号，序列号是唯一的。 HFI更新元组内的计数值，其包括第一GSM分组的序列号和计数值以及为GSM消息接收的每个后续GSM分组。通过将计数值与从分组报头检索的计数总数进行比较，HFI确定接收到GSM消息的完成。

18. 发明授权

US08127300B2 Hardware based dynamic load balancing of message passing interface tasks 失效
标题翻译：基于硬件的动态负载平衡消息传递接口任务
公开(公告)号：US08127300B2
公开(公告)日：2012-02-28
申请号：US11846119
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46 , G06F15/173
CPC分类号： G06F9/522 , G06F9/5083
摘要： Mechanisms for providing hardware based dynamic load balancing of message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的机制。提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。

19. 发明申请

US20110022773A1 Fine Grained Cache Allocation 有权
标题翻译：细粒度缓存分配
公开(公告)号：US20110022773A1
公开(公告)日：2011-01-27
申请号：US12509752
申请日：2009-07-27
申请人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/084 , G06F12/0864 , G06F12/126 , Y02D10/13
摘要： A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.
摘要翻译：在虚拟机监视器中提供了用于共享高速缓存中的细粒度高速缓存分配的机制。该机制将高速缓存标签分成最高有效位（MSB）部分和最低有效位（LSB）部分。标签的MSB部分在一组中的高速缓存行之间共享。标签的LSB部分是私有的，每个缓存行一个。该机制允许软件将缓存中的标签的MSB部分设置为分配高速缓存行集合。高速缓存控制器基于标签的MSB部分来确定高速缓存行是否被锁定。

20. 发明申请

US20090199046A1 Mechanism to Perform Debugging of Global Shared Memory (GSM) Operations 失效
标题翻译：执行全局共享内存（GSM）操作调试的机制
公开(公告)号：US20090199046A1
公开(公告)日：2009-08-06
申请号：US12024585
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F11/00
CPC分类号： G06F13/385
摘要： A host fabric interface (HFI) enables debugging of global shared memory (GSM) operations received at a local node from a network fabric. The local node has a memory management unit (MMU), which provides an effective address to real address (EA-to-RA) translation table that is utilized by the HFI to evaluate when EAs of GSM operations/data from a received GSM packet is memory-mapped to RAs of the local memory. The HFI retrieves the EA associated with a GSM operation/data within a received GSM packet. The HFI forwards the EA to the MMU, which determines when the EA is mapped to RAs within the local memory for the local task. The HFI processing logic enables processing of the GSM packet only when the EA of the GSM operation/data within the GSM packet is an EA that has a local RA translation. Non-matching EAs result in an error condition that requires debugging.
摘要翻译：主机结构接口（HFI）可以调试从网络结构在本地节点接收到的全局共享存储器（GSM）操作。本地节点具有存储器管理单元（MMU），该存储器管理单元（MMU）为HFI用于实际地址（EA-to-RA）转换表提供有效地址，以评估来自接收到的GSM分组的GSM操作/数据的EAs是否为内存映射到本地内存的RA。 HFI检索与接收的GSM分组内的GSM操作/数据相关联的EA。 HFI将EA转发到MMU，该MMU确定EA何时映射到本地内存中的本地任务的RA。 HFI处理逻辑仅当GSM操作的EA / GSM分组内的数据是具有本地RA转换的EA时才能处理GSM分组。不匹配的EA会导致需要调试的错误条件。

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