专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20060282237A1 Fixed point integer division techniques for AC/DC prediction in video coding devices 有权
标题翻译：用于视频编码设备中AC / DC预测的定点整数除法技术
公开(公告)号：US20060282237A1
公开(公告)日：2006-12-14
申请号：US11137069
申请日：2005-05-25
申请人： Shu Xiao , Junchen Du , Tao Shen
发明人： Shu Xiao , Junchen Du , Tao Shen
IPC分类号： G06F17/10
CPC分类号： H04N19/18 , G06F7/4873 , G06F7/49963 , G06F7/535 , G06F2101/12 , G06F2207/5356 , H04N19/42 , H04N19/593 , H04N19/61
摘要： The disclosure describes a method for performing a fixed point calculation of a floating point operation (A // B) in a coding device, wherein A // B represents integer division of A divided by B rounded to a nearest integer. The method may comprise selecting an entry from a lookup table (LUT) having entries generated as an inverse function of an index B, wherein B defines a range of values that includes every DC scalar value and every quantization parameter associated with a coding standard, and calculating A // B for coding according to the coding standard based on values A, B1 and B2, wherein B1 and B2 comprise high and low portions of the selected entry of the LUT. The techniques may simplify digital signal processor (DSP) implementations of video coders, and are specifically useful for MPEG-4 coders and possibly others.
摘要翻译：本公开描述了一种用于在编码装置中执行浮点运算（A // B）的固定点计算的方法，其中A // B表示A除以被舍入为最接近整数的B的整数除法。该方法可以包括从具有作为索引B的反函数生成的条目的查找表（LUT）中选择条目，其中B定义包括每个DC标量值和与编码标准相关联的每个量化参数的值的范围，以及基于值A，B 1和B 2，根据编码标准计算A // B进行编码，其中B 1和B 2包括LUT的所选条目的高和低部分。这些技术可以简化视频编码器的数字信号处理器（DSP）实现，并且对MPEG-4编码器和可能的其它编码器特别有用。

12. 发明授权

US06845135B2 Cascaded biquad infinite impulse response filter 有权
标题翻译：级联双二阶无限脉冲响应滤波器
公开(公告)号：US06845135B2
公开(公告)日：2005-01-18
申请号：US09766735
申请日：2001-01-22
申请人： Junchen Du
发明人： Junchen Du
IPC分类号： H03H17/04 , H04B1/10
CPC分类号： H03H17/04
摘要： An improved cascaded biquad infinite impulse response (IIR) filter structure is provided. The IIR filter of the invention may be implemented in a digital signal processor (DSP) such as a very long instruction word (VLIW) type DSP, as well as other processing circuitry, e.g., an integrated circuit. The new filter structure, among other advantages, overcomes the bottleneck condition known to occur in the updating operation of the w2(n−1) state of a conventional cascaded biquad IIR filter. In one illustrative implementation of the invention, this is accomplished by adding a single 32-bit intermediate state thus providing a cascaded biquad IIR filter structure such that the w2(n−1) state may be updated one clock cycle earlier. Thus, in a StarCore SC140 DSP example where a corresponding conventional cascaded biquad IIR filter structure executes at seven cycles per input sample, the improved cascaded biquad IIR filter structure of the present invention executes at six cycles per input sample. Therefore, without losing any precision, the kernel cycle count associated with the improved cascaded biquad IIR filter structure is advantageously reduced by 14 percent. Such a reduction in kernel count translates to a proportional increase in the processing speed of the DSP or other processing circuitry with which it is implemented.
摘要翻译：提供了改进的级联双二阶无限脉冲响应（IIR）滤波器结构。本发明的IIR滤波器可以在诸如非常长的指令字（VLIW）型DSP的数字信号处理器（DSP）以及诸如集成电路的其它处理电路中实现。新的滤波器结构以及其他优点克服了已知在常规级联双二阶IIR滤波器的w2（n-1）状态的更新操作中发生的瓶颈状况。在本发明的一个说明性实现中，这通过添加单个32位中间状态来实现，从而提供级联的双二阶IIR滤波器结构，使得可以更早地一个时钟周期更新w2（n-1）状态。因此，在StarCore SC140 DSP示例中，相应的常规级联双二阶IIR滤波器结构在每个输入样本的七个周期上执行，本发明的改进的级联biquad IIR滤波器结构在每个输入样本六个周期执行。因此，在不损失任何精度的情况下，与改进的级联biquad IIR滤波器结构相关联的核周期计数有利地减少了14％。这样的内核计数的减少转化为DSP或其实施的其他处理电路的处理速度的比例增加。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式