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11. 发明申请

US20100031215A1 System and Method for Improved Placement in Custom VLSI Circuit Design with Schematic-Driven Placement 有权
标题翻译：使用原理图驱动的放置在自定义VLSI电路设计中改进放置的系统和方法
公开(公告)号：US20100031215A1
公开(公告)日：2010-02-04
申请号：US12183898
申请日：2008-07-31
申请人： William D. Ramsour , Samuel I. Ward , Jun Zhou
发明人： William D. Ramsour , Samuel I. Ward , Jun Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for generating an electronic circuit layout with placed circuit elements receives a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements, wherein the first placement parameters comprise a cell horizontal position, a cell vertical stacking position, and a cell vertical adjacent spacing. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method assigns first absolute placement coordinates for each of the plurality of circuit elements based on the first placement parameters and the design parameters. The method defines and performs an adjustment operation on the placement parameters of a selected subset of circuit elements, generating adjusted placement parameters. The method assigns second absolute placement coordinates based on the first placement parameters, the design parameters, and the adjusted placement parameters and generates an electronic circuit layout with placed circuit elements based on the second absolute placement coordinates.
摘要翻译：用于产生具有放置的电路元件的电子电路布局的方法接收用户提供的原理图，用户提供了包括多个电路元件的示意图，每个电路元件包括一般参数。该方法将多个第一放置参数与多个电路元件中的每一个相关联，其中第一放置参数包括单元水平位置，单元垂直堆叠位置和单元垂直相邻间隔。该方法从设计库检索与多个电路元件中的至少一个相关联的设计参数。该方法基于第一放置参数和设计参数为多个电路元件中的每一个分配第一绝对放置坐标。该方法定义并执行对所选择的电路元件子集的放置参数的调整操作，生成调整的放置参数。该方法基于第一放置参数，设计参数和调整的放置参数分配第二绝对放置坐标，并且基于第二绝对放置坐标生成具有放置的电路元件的电子电路布局。

12. 发明申请

US20090013227A1 Method Using Non-Linear Compression to Generate a Set of Test Vectors for Use in Scan Testing an Integrated Circuit 有权
标题翻译：使用非线性压缩生成用于扫描测试集成电路的一组测试向量的方法
公开(公告)号：US20090013227A1
公开(公告)日：2009-01-08
申请号：US11773578
申请日：2007-07-05
申请人： Gahn W. Krishnakalin , Emiliano Lozano , Bao G. Truong , Samuel I. Ward
发明人： Gahn W. Krishnakalin , Emiliano Lozano , Bao G. Truong , Samuel I. Ward
IPC分类号： G01R31/3183
CPC分类号： G01R31/318547
摘要： A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to at least one of a plurality of decoders, wherein each decoder is adapted to recognize the coding scheme represented by one of the bit patterns. A decoder is operated to generate one of the test vectors, when the decoder receives the block corresponding to the generated test vector, and recognizes the coding scheme that is encoded by the received data block.
摘要翻译：提供了一种使用非线性数据压缩的方法，以便产生用于在集成电路的扫描测试中使用的一组测试向量。该方法包括以下步骤：初始设计测试向量集合，并为每个测试向量选择多个可用编码方案之一。该方法还包括操作随机模式发生器以产生数据块，每个数据块对应于一个测试向量，其中与给定测试向量相对应的数据块用表示给定测试向量的编码方案的比特模式进行编码。相应的数据块还具有小于给定测试向量的位长度的位长度。每个数据块被路由到多个解码器中的至少一个，其中每个解码器适于识别由一个位模式表示的编码方案。当解码器接收对应于所生成的测试向量的块并且识别由接收的数据块编码的编码方案时，操作解码器以产生测试向量之一。

13. 发明申请

US20080263418A1 System and Method for Adaptive Nonlinear Test Vector Compression 失效
标题翻译：自适应非线性测试向量压缩的系统和方法
公开(公告)号：US20080263418A1
公开(公告)日：2008-10-23
申请号：US11738746
申请日：2007-04-23
申请人： Samuel I. Ward
发明人： Samuel I. Ward
IPC分类号： G01R31/28
CPC分类号： G01R31/31921
摘要： A system comprises a decompressor configured to receive an input test vector and to generate an output vector in response to the input test vector. A decoder couples to the decompressor and comprises a reset pattern detector, a lookup table, and control logic. The reset pattern detector (RPD) is configured to scan the output vector to identify a predetermined reset pattern. The control logic couples to the RPD and the lookup table and is configured to direct operation of the lookup table in a first mode or a second mode based on whether the output vector comprises the predetermined reset pattern, as identified by the RPD. The lookup table is configured to receive the output vector, to operate in the first mode, comprising storing one of a plurality of codeword sets, each codeword set comprising a plurality of pairs of codewords and associated data; and to operate in the second mode, comprising generating test data blocks in response to identified codewords in the output vector.A method for adaptive test data compression includes receiving an input vector. The input vector is decompressed to generate an output vector. A determination is made whether the output vector comprises a reset pattern. In the event the output vector comprises a reset pattern, one of a plurality of codeword sets is loaded into a lookup table; each codeword set comprising a plurality of pairs of codewords and associated data. In the event the output vector does not comprise a reset pattern, codewords in the output vector are identified and test data blocks are generated in response to identified codewords.
摘要翻译：系统包括解压缩器，其被配置为接收输入测试向量并响应于输入测试向量生成输出向量。解码器耦合到解压缩器并且包括复位模式检测器，查找表和控制逻辑。复位图案检测器（RPD）被配置为扫描输出向量以识别预定的复位模式。控制逻辑耦合到RPD和查找表，并且被配置为基于由RPD识别的输出向量是否包括预定的重置模式，以第一模式或第二模式来引导查找表的操作。查找表被配置为接收输出向量以在第一模式中操作，包括存储多个码字集合中的一个，每个码字集合包括多对码字和相关联的数据; 并且在第二模式中操作，包括响应于输出向量中识别的码字生成测试数据块。用于自适应测试数据压缩的方法包括接收输入向量。输入向量被解压缩以产生输出向量。确定输出矢量是否包括复位模式。在输出矢量包括复位模式的情况下，多个码字集合中的一个被加载到查找表中; 每个码字集合包括多对码字和相关联的数据。在输出向量不包括复位模式的情况下，识别输出向量中的码字，并且响应于所识别的码字生成测试数据块。

14. 发明授权

US09171286B2 Recording events in a virtual world 有权
标题翻译：在虚拟世界中记录事件
公开(公告)号：US09171286B2
公开(公告)日：2015-10-27
申请号：US13620810
申请日：2012-09-15
申请人： Kulvir S. Bhogal , Lisa Seacat DeLuca , Timothy J. Eby , Samuel I. Ward
发明人： Kulvir S. Bhogal , Lisa Seacat DeLuca , Timothy J. Eby , Samuel I. Ward
IPC分类号： G06F3/048 , G06F3/01 , G06F9/44 , G06Q10/10 , A63F13/30 , G06N3/00
CPC分类号： H04N5/91 , A63F2300/5553 , G06N3/006 , G06Q10/10
摘要： Systems, methods and articles of manufacture are disclosed for recording events occurring in a virtual world. In one embodiment, properties of events previously recorded and/or attended by a user may be identified. Recording criteria for the user may be derived from the identified properties. Upon identifying an event satisfying the recording criteria, the event may be recorded. The recorded event may be played back at the convenience of the user.
摘要翻译：公开了用于记录在虚拟世界中发生的事件的系统，方法和制品。在一个实施例中，可以识别先前由用户记录和/或参与的事件的属性。可以从所识别的属性导出用户的记录标准。在识别满足记录标准的事件时，可以记录事件。记录的事件可以在用户方便的情况下重放。

15. 发明申请

US20140026110A1 GENERATING AND SELECTING BIT-STACK CANDIDATES FROM A GRAPH USING DYNAMIC PROGRAMMING 失效
标题翻译：使用动态编程从图形生成和选择位堆栈候选
公开(公告)号：US20140026110A1
公开(公告)日：2014-01-23
申请号：US13552919
申请日：2012-07-19
申请人： Samuel I. Ward
发明人： Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Bit stacks of an integrated circuit design are identified in a netlist by analyzing cell clusters. Candidate bit stacks are generated for each cluster using cone tracing, and wirelength costs are calculated for the candidate bit stacks based on the cells' locations from a previous (e.g., global) placement. The bit stack partition having a minimum total wirelength cost is selected for the final bit stacks. The invention can find K bit stacks in a cell cluster having N input cells and M output cells, where K, N and M are all different. The method is advantageously made timing aware by weighting connections between cells using weights based on timing information. Once the final bit stacks have been identified, the information can be included in the netlist and passed to a datapath placer for optimized placement.
摘要翻译：通过分析单元集群，在网表中识别集成电路设计的位堆栈。使用锥形跟踪为每个集群生成候选位堆栈，并且基于来自先前（例如，全局）位置的单元格的位置为候选位堆栈计算电线长度成本。为最终位堆栈选择具有最小总线长度成本的位堆栈分区。本发明可以在具有N个输入单元和M个输出单元的单元簇中找到K个位堆栈，其中K，N和M都不同。该方法有利地通过使用基于定时信息的权重来加权小区之间的连接而使定时感知。一旦确定了最终位堆栈，信息就可以被包含在网表中，并被传递给数据路径放置器以优化放置。

16. 发明授权

US08028265B2 System and method for improved placement in custom VLSI circuit design with schematic-driven placement 有权
标题翻译：系统和方法，用于改进在具有原理图驱动放置的定制VLSI电路设计中的放置
公开(公告)号：US08028265B2
公开(公告)日：2011-09-27
申请号：US12183898
申请日：2008-07-31
申请人： William D. Ramsour , Samuel I. Ward , Jun Zhou
发明人： William D. Ramsour , Samuel I. Ward , Jun Zhou
IPC分类号： G06F17/50 , G06F15/04
CPC分类号： G06F17/5072
摘要： A method for generating an electronic circuit layout with placed circuit elements receives a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements, wherein the first placement parameters comprise a cell horizontal position, a cell vertical stacking position, and a cell vertical adjacent spacing. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method assigns first absolute placement coordinates for each of the plurality of circuit elements based on the first placement parameters and the design parameters. The method defines and performs an adjustment operation on the placement parameters of a selected subset of circuit elements, generating adjusted placement parameters. The method assigns second absolute placement coordinates based on the first placement parameters, the design parameters, and the adjusted placement parameters and generates an electronic circuit layout with placed circuit elements based on the second absolute placement coordinates.
摘要翻译：用于产生具有放置的电路元件的电子电路布局的方法接收用户提供的原理图，用户提供了包括多个电路元件的示意图，每个电路元件包括一般参数。该方法将多个第一放置参数与多个电路元件中的每一个相关联，其中第一放置参数包括单元水平位置，单元垂直堆叠位置和单元垂直相邻间隔。该方法从设计库检索与多个电路元件中的至少一个相关联的设计参数。该方法基于第一放置参数和设计参数为多个电路元件中的每一个分配第一绝对放置坐标。该方法定义并执行对所选择的电路元件子集的放置参数的调整操作，生成调整的放置参数。该方法基于第一放置参数，设计参数和调整的放置参数分配第二绝对放置坐标，并且基于第二绝对放置坐标生成具有放置的电路元件的电子电路布局。

17. 发明申请

US20110119581A1 RECORDING EVENTS IN A VIRTUAL WORLD 失效
标题翻译：虚拟世界纪录活动
公开(公告)号：US20110119581A1
公开(公告)日：2011-05-19
申请号：US12622205
申请日：2009-11-19
申请人： Kulvir S. Bhogal , Lisa Seacat DeLuca , Timothy J. Eby , Samuel I. Ward
发明人： Kulvir S. Bhogal , Lisa Seacat DeLuca , Timothy J. Eby , Samuel I. Ward
IPC分类号： G06F3/00 , G06F3/048
CPC分类号： H04N5/91 , A63F2300/5553 , G06N3/006 , G06Q10/10
摘要： Systems, methods and articles of manufacture are disclosed for recording events occurring in a virtual world. In one embodiment, properties of events previously recorded and/or attended by a user may be identified. Recording criteria for the user may be derived from the identified properties. Upon identifying an event satisfying the recording criteria, the event may be recorded. The recorded event may be played back at the convenience of the user.
摘要翻译：公开了用于记录在虚拟世界中发生的事件的系统，方法和制品。在一个实施例中，可以识别先前由用户记录和/或参与的事件的属性。可以从所识别的属性导出用户的记录标准。在识别满足记录标准的事件时，可以记录事件。记录的事件可以在用户方便的情况下重放。

18. 发明申请

US20100179784A1 TEST PATTERN COMPRESSION 失效
标题翻译：测试图案压缩
公开(公告)号：US20100179784A1
公开(公告)日：2010-07-15
申请号：US12354063
申请日：2009-01-15
申请人： Patrick R. Crosby , Daniel W. Cervantes , Johnny J. LeBlanc , Samuel I. Ward
发明人： Patrick R. Crosby , Daniel W. Cervantes , Johnny J. LeBlanc , Samuel I. Ward
IPC分类号： G01R31/00 , G01R31/02
CPC分类号： G01R31/318547
摘要： A method for test pattern compression generates a first test pattern comprising a plurality of bits. The method identifies bits comprising a don't-care bit value in the first test pattern and replaces the identified bit values with random bit values, to generate a second test pattern. The method determines a fault coverage level of the second test pattern. In the event the determined fault coverage level of the second test pattern exceeds a predetermined individual test pattern fault coverage level, for at least one bit position in the second test pattern corresponding to a replaced identified bit value and detecting at least one fault, the method exchanges the don't care value in the bit position in the first test pattern with the bit value in the corresponding bit position in the second test pattern. The method merges subsequent test patterns that increase fault coverage with the second test pattern.
摘要翻译：测试图案压缩的方法产生包括多个位的第一测试图案。该方法识别在第一测试模式中包含不关心位值的位，并且用随机位值替换所识别的位值，以产生第二测试模式。该方法确定第二测试模式的故障覆盖水平。在第二测试模式的所确定的故障覆盖水平超过预定的单独测试模式故障覆盖水平的情况下，对于与替换的所识别的位值相对应的第二测试模式中的至少一个位位置并检测至少一个故障，该方法在第一测试模式中的位位置交换不关心值的第二测试模式中相应位位置的位值。该方法将随后的测试模式合并，以增加第二个测试模式的故障覆盖。

19. 发明授权

US08589848B2 Datapath placement using tiered assignment 有权
标题翻译： Datapath放置使用分层分配
公开(公告)号：US08589848B2
公开(公告)日：2013-11-19
申请号：US13451382
申请日：2012-04-19
申请人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information.
摘要翻译：数据路径布局定义了单元格集群的布局集合的层次，将单元格分配给由数据路径宽度约束的层，然后在每个层中排序单元格。使用基于机器学习的数据路径提取来识别群集。数据路径宽度通过计算群集中的单元格的边界框的大小来确定。使用从集群的输入单元开始的宽度优先搜索来标识放置集。最初使用逻辑深度分配定义层次。可以通过从下一较高层拉动单元以填充空位或通过将多余单元推入下一较高层来将单元分配给层。根据线长成本函数，使用贪心小区分配在每个层中对单元进行排序。数据路径放置可以是迭代过程的一部分，其基于计算的拥塞信息将扩展约束应用于集群。

20. 发明申请

US20130283225A1 DATAPATH PLACEMENT USING TIERED ASSIGNMENT 有权
标题翻译：使用方式分配的DATAPATH放置
公开(公告)号：US20130283225A1
公开(公告)日：2013-10-24
申请号：US13451382
申请日：2012-04-19
申请人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information.
摘要翻译：数据路径布局定义了单元格集群的布局集合的层次，将单元格分配给由数据路径宽度约束的层，然后在每个层中排序单元格。使用基于机器学习的数据路径提取来识别群集。数据路径宽度通过计算群集中的单元格的边界框的大小来确定。使用从集群的输入单元开始的宽度优先搜索来标识放置集。最初使用逻辑深度分配定义层次。可以通过从下一较高层拉动单元以填充空位或通过将多余单元推入下一较高层来将单元分配给层。根据线长成本函数，使用贪心小区分配在每个层中对单元进行排序。数据路径放置可以是迭代过程的一部分，其基于计算的拥塞信息将扩展约束应用于集群。

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