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11. 发明申请

US20090063702A1 CROSSBAR APPARATUS FOR A FORWARDING TABLE MEMORY IN A ROUTER 有权
标题翻译：用于在路由器中转发表存储器的交叉设备
公开(公告)号：US20090063702A1
公开(公告)日：2009-03-05
申请号：US12260841
申请日：2008-10-29
申请人： John C. Holst , William L. Lynch
发明人： John C. Holst , William L. Lynch
IPC分类号： G06F13/16 , G06F12/08 , G06F15/16
CPC分类号： H04L12/66 , H04L45/00 , H04L45/54 , H04L45/60
摘要： A router including a lookup execution unit including a plurality of stages, a forwarding table memory arranged in hierarchy including addressable sectors, blocks, and entries, and a crossbar having an address crossbar for selectively coupling one of the plurality of stages to a sector of the memory so that data from the sector can be read. In one example, any one of the stages of the plurality of stages may be selectively and dynamically coupled with any one of the sectors of the forwarding table memory for providing an address to a particular sector of the memory to read data therefrom.
摘要翻译：包括包括多个级的查找执行单元的路由器，分层布置的转发表存储器，包括可寻址扇区，块和条目，以及具有地址横栏的交叉开关，用于选择性地将多个级中的一个级联到存储器，使得可以读取来自扇区的数据。在一个示例中，多个级中的任何一级可以选择性地和动态地耦合到转发表存储器的任何一个扇区，以便向存储器的特定扇区提供地址以从其读取数据。

12. 发明申请

US20090046724A1 METHOD FOR COMPRESSING ROUTE DATA IN A ROUTER 有权
标题翻译：在路由器中压缩路由数据的方法
公开(公告)号：US20090046724A1
公开(公告)日：2009-02-19
申请号：US12252079
申请日：2008-10-15
申请人： William L. Lynch , Srihari Ramachandra Sangli
发明人： William L. Lynch , Srihari Ramachandra Sangli
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L45/54 , H04L49/3009
摘要： A method for a router having a routing table and a forwarding table. In an embodiment, the method includes creating an entry for use in the forwarding table, the entry corresponding to multiple entries of the routing table. The entry may correspond to a set of entries of the routing table which specify overlapping IP addresses and a same next hop router, in one example. In another example, the entry may be an aggregate entry corresponding to a set of entries of the routing table which specify the same next hop router.
摘要翻译：一种具有路由表和转发表的路由器的方法。在一个实施例中，该方法包括创建用于转发表中的条目，该条目对应于路由表的多个条目。在一个示例中，条目可以对应于路由表的一组条目，其指定重叠的IP地址和相同的下一跳路由器。在另一示例中，条目可以是对应于指定相同下一跳路由器的路由表的一组条目的聚合条目。

13. 发明授权

US07450438B1 Crossbar apparatus for a forwarding table memory in a router 有权
标题翻译：用于路由器中的转发表存储器的交叉开关设备
公开(公告)号：US07450438B1
公开(公告)日：2008-11-11
申请号：US10418634
申请日：2003-04-17
申请人： John C. Holst , William L. Lynch
发明人： John C. Holst , William L. Lynch
IPC分类号： G11C11/34
CPC分类号： H04L12/66 , H04L45/00 , H04L45/54 , H04L45/60
摘要： A router including a lookup execution unit including a plurality of stages, a forwarding table memory arranged in hierarchy including addressable sectors, blocks, and entries, and a crossbar having an address crossbar for selectively coupling one of the plurality of stages to a sector of the memory so that data from the sector can be read. In one example, any one of the stages of the plurality of stages may be selectively and dynamically coupled with any one of the sectors of the forwarding table memory for providing an address to a particular sector of the memory to read data therefrom.
摘要翻译：包括包括多个级的查找执行单元的路由器，分层布置的转发表存储器，包括可寻址扇区，块和条目，以及具有地址横栏的交叉开关，用于选择性地将多个级中的一个级联到存储器，使得可以读取来自扇区的数据。在一个示例中，多个级中的任何一级可以选择性地和动态地耦合到转发表存储器的任何一个扇区，以便向存储器的特定扇区提供地址以从其读取数据。

14. 发明授权

US6076147A Non-inclusive cache system using pipelined snoop bus 失效
标题翻译：使用流水线监听总线的非包容性缓存系统
公开(公告)号：US6076147A
公开(公告)日：2000-06-13
申请号：US881745
申请日：1997-06-24
申请人： William L. Lynch , Al Yamauchi
发明人： William L. Lynch , Al Yamauchi
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data which is absent from the external cache. A pipelined snoop bus is ported to each of the set of tags of the plurality of on-chip caches and transmits a snoop address to the plurality of on-chip caches. A system interface unit is responsive to a received snoop request to scan the external cache and to apply the snoop address of the snoop request to the pipelined snoop bus. A plurality of response signal lines respectively extend from the plurality of on-chip caches to the system interface unit, each of the signal lines for transmitting a snoop response from a corresponding one of the on-board caches to the system interface unit. The set of tags can be implemented by dual-porting the cache tags, or by providing a duplicate and dedicated set of snoop tags.
摘要翻译：非包容性缓存系统包括外部高速缓存和多个片上高速缓存，每个具有与之相关联的一组标签，片上高速缓存中的至少一个包括外部高速缓存中不存在的数据。流水线窥探总线被移植到多个片上高速缓存中的每组标签中，并将一个窥探地址发送到多个片上高速缓存。系统接口单元响应于所接收的窥探请求来扫描外部高速缓存并将窥探请求的窥探地址应用于流水线窥探总线。多个响应信号线分别从多个片上高速缓存延伸到系统接口单元，每个信号线用于从相应的板载高速缓存发送窥探响应到系统接口单元。标签集可以通过双端口缓存标签来实现，或者通过提供一组重复的和专用的snoop标签集来实现。

15. 发明授权

US07453883B1 Method for compressing route data in a router 有权
标题翻译：路由器中路由数据压缩的方法
公开(公告)号：US07453883B1
公开(公告)日：2008-11-18
申请号：US10414137
申请日：2003-04-14
申请人： William L. Lynch , Srihari Ramachandra Sangli
发明人： William L. Lynch , Srihari Ramachandra Sangli
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L45/54 , H04L49/3009
摘要： A method for a router having a routing table and a forwarding table. In an embodiment, the method includes creating an entry for use in the forwarding table, the entry corresponding to multiple entries of the routing table. The entry may correspond to a set of entries of the routing table which specify overlapping IP addresses and a same next hop router, in one example. In another example, the entry may be an aggregate entry corresponding to a set of entries of the routing table which specify the same next hop router.
摘要翻译：一种具有路由表和转发表的路由器的方法。在一个实施例中，该方法包括创建用于转发表中的条目，该条目对应于路由表的多个条目。在一个示例中，条目可以对应于路由表的一组条目，其指定重叠的IP地址和相同的下一跳路由器。在另一示例中，条目可以是对应于指定相同下一跳路由器的路由表的一组条目的聚合条目。

16. 发明授权

US06164840A Ensuring consistency of an instruction cache with a store cache check and an execution blocking flush instruction in an instruction queue 失效
标题翻译：确保指令高速缓存与指令队列中的存储高速缓存检查和执行阻塞刷新指令的一致性
公开(公告)号：US06164840A
公开(公告)日：2000-12-26
申请号：US881106
申请日：1997-06-24
申请人： William L. Lynch
发明人： William L. Lynch
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3812 , G06F9/30047 , G06F12/0848
摘要： A method of ensuring instruction cache consistency in a processor includes executing a flush instruction whenever a program executed by the processor stores data to a given data address and, subsequently, executes another instruction requiring a data fetch from the same address. According to this method, a write cache prevents any addressed instruction from residing in the write cache and the instruction cache at the same time. Thus, when an instruction having a store address not already present in the write cache is retired to the write cache, the write cache instructs the instruction cache to invalidate any data stored therein having a same address. The flush instruction prevents execution of any other instructions after the store at least until the store to the memory address has been allocated to a write cache of the processor, thus enabling the write cache to invalidate the subsequent instruction at the same address in the instruction cache. The method insures instruction cache consistency without the need to check every store against the instruction cache.
摘要翻译：确保处理器中的指令高速缓存一致性的方法包括每当由处理器执行的程序将数据存储到给定的数据地址时执行刷新指令，并且随后从相同的地址执行需要数据取出的另一指令。根据该方法，写入高速缓存防止任何寻址的指令同时驻留在写入高速缓存和指令高速缓存中。因此，当具有写入高速缓存中尚未存在的存储地址的指令退出到写入高速缓存时，写入高速缓存指示指令高速缓存使其中存储的具有相同地址的数据无效。闪存指令防止在存储之后执行任何其他指令，直到存储到存储器地址的存储已被分配给处理器的写入高速缓存，从而使得写入高速缓存能够使指令高速缓存中的相同地址处的后续指令无效。该方法确保指令高速缓存一致性，而不需要根据指令高速缓存检查每个存储。

17. 发明授权

US6016532A Method for handling data cache misses using help instructions 失效
标题翻译：使用帮助说明处理数据高速缓存未命中的方法
公开(公告)号：US6016532A
公开(公告)日：2000-01-18
申请号：US884066
申请日：1997-06-27
申请人： William L. Lynch , Gary R. Lauterbach
发明人： William L. Lynch , Gary R. Lauterbach
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F17/30
CPC分类号： G06F9/30043 , G06F9/383 , G06F9/3875
摘要： A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a fashion similar to the instruction which caused the miss (the "miss instruction"). The help instructions use the source operands of the miss instruction to form the miss address, thereby providing the fill address using the same elements which are used to calculate cache access addresses. In one embodiment, a fill help instruction and a bypass help instruction are generated. The fill help instruction provides the input address to the data cache during the clock cycle in which the fill data arrives. The appropriate row of the data cache is thereby selected for storing the fill data. The bypass help instruction is dispatched to arrive in a second pipeline stage different from the stage occupied by the fill help instruction. The bypass help instruction causes the datum requested by the miss instruction to be forwarded to the destination of the miss instruction.
摘要翻译：微处理器被配置为响应于数据高速缓存未命中产生帮助指令。帮助指令以类似于导致未命中的指令（“未命令指令”）的方式流过微处理器的指令处理流水线。帮助指令使用miss指令的源操作数来形成未命中地址，从而使用用于计算缓存访问地址的相同元素来提供填充地址。在一个实施例中，生成填充帮助指令和旁路帮助指令。填充帮助指令在填充数据到达的时钟周期期间向数据高速缓存提供输入地址。由此选择数据高速缓存的适当行以存储填充数据。旁路帮助指令被调度到不同于填充帮助指令占据的阶段的第二流水线阶段。旁路帮助指令导致由miss指令请求的数据被转发到未命中指令的目的地。

18. 发明授权

US5754819A Low-latency memory indexing method and structure 失效
标题翻译：低延迟内存索引方法和结构
公开(公告)号：US5754819A
公开(公告)日：1998-05-19
申请号：US282525
申请日：1994-07-28
申请人： William L. Lynch , Gary R. Lauterbach
发明人： William L. Lynch , Gary R. Lauterbach
IPC分类号： G11C11/413 , G06F12/02 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0864
摘要： A significant reduction in the latency between the time the addressed components of memory are ready and the time addressed data is available to the address components of memory is achieved by processing the raw address information faster than the addition used in the prior art. XOR memory addressing replaces the addition of the base and offset address components with an XOR operation, eliminating carry propagation and reducing overall latency. In another embodiment, a sum-addressed memory (SAM) also eliminates the carry propagation and thus reduce the latency while providing the correct base+offset index to access the memory word line corresponding to the correct addition; thus a SAM causes no XOR duplicate problems.
摘要翻译：通过比现有技术中使用的添加更快地处理原始地址信息来实现存储器的寻址组件准备好的时间和时间寻址数据对存储器的地址组件可用的等待时间的显着减少。 XOR存储器寻址用XOR操作替代了基本和偏移地址组件的添加，消除了进位传播并减少了总体延迟。在另一个实施例中，和寻址存储器（SAM）也消除了进位传播，从而减少延迟，同时提供正确的基极+偏移索引来访问对应于正确相加的存储器字线; 因此SAM不会导致XOR重复的问题。

19. 发明授权

US5649126A Parallel signal bus with reduced miller effect capacitance 失效
标题翻译：并联信号母线，具有降低的磨机效应电容
公开(公告)号：US5649126A
公开(公告)日：1997-07-15
申请号：US566842
申请日：1995-12-04
申请人： William L. Lynch
发明人： William L. Lynch
IPC分类号： G06F13/40
CPC分类号： G06F13/4077
摘要： A parallel signal bus for conveying a plurality of logic signals with reduced Miller effect capacitance includes adjacent, parallel signal lines with inverting buffer amplifiers whose respective positions are staggered both longitudinally along the signal lines and latitudinally with respect to their adjacent signal lines. With such a staggered configuration, the resulting Miller effect capacitance which would otherwise result from adjacent signal lines being driven at opposing polarities is reduced, on average, by approximately half.
摘要翻译：用于传送具有减小的米勒效应电容的多个逻辑信号的并行信号总线包括具有反相缓冲放大器的相邻的并行信号线，其反相缓冲放大器的相应位置沿着信号线沿纵向交错并相对于它们的相邻的信号线横向交错。通过这样的交错配置，由相邻的信号线产生的所产生的米勒效应电容平均大约减小一半。

20. 发明授权

US06317810B1 Microprocessor having a prefetch cache 失效
标题翻译：具有预取缓存的微处理器
公开(公告)号：US06317810B1
公开(公告)日：2001-11-13
申请号：US08882691
申请日：1997-06-25
申请人： Herbert Lopez-Aguado , Denise Chiacchia , William L. Lynch , Gary Lauterbach
发明人： Herbert Lopez-Aguado , Denise Chiacchia , William L. Lynch , Gary Lauterbach
IPC分类号： G06F1208
CPC分类号： G06F9/3802 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F9/3861 , G06F12/0862 , G06F2212/6022 , G06F2212/6028
摘要： A central processing unit of a computer includes a single-ported data cache and a dual-ported prefetch cache. The data cache accommodates a first pipeline and the prefetch cache, which is much smaller than the data cache, accommodates both the first pipeline and a second pipeline. If a data cache miss occurs, a row of data corresponding to the specified address is stored in the data cache and the prefetch cache. Thereafter, if a prefetch cache hit occurs, a row of data corresponding to a prefetch address is loaded into the prefetch cache. The prefetch address may, for instance, be generated by adding a fixed increment to the specified address. This operation frequently results in the prefetch cache storing data soon requested by a computer program. When this condition is achieved, the data corresponding to the subsequent address request is rapidly retrieved from cache memory without incurring memory latencies associated with the external cache, the primary memory, and the secondary memory. In this manner, the prefetch cache of the present invention facilitates improved memory latencies. Further, the prefetch cache allows for two data requests to be processed simultaneously without a corresponding two-fold increase in cost of data cache memory.
摘要翻译：计算机的中央处理单元包括单端口数据高速缓存和双端口预取缓存。数据高速缓存容纳第一流水线，并且比数据高速缓存小得多的预取缓存容纳第一流水线和第二流水线。如果发生数据高速缓存未命中，则与指定地址对应的数据行存储在数据高速缓存和预取缓存中。此后，如果发生预取缓存命中，则将与预取地址对应的数据行加载到预取高速缓存中。预取地址可以例如通过向指定的地址添加固定的增量来生成。此操作经常导致预取缓存存储计算机程序很快请求的数据。当达到这种条件时，与高速缓冲存储器快速地检索对应于后续地址请求的数据，而不会引起与外部高速缓存，主存储器和辅助存储器相关联的存储器延迟。以这种方式，本发明的预取高速缓存有利于改进的存储器延迟。此外，预取缓存允许同时处理两个数据请求，而数据高速缓冲存储器的成本增加相应的两倍。

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