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11. 发明授权

US08507333B2 Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device 失效
标题翻译：具有串联场效应晶体管和集成电压均衡的集成电路器件及其形成方法
公开(公告)号：US08507333B2
公开(公告)日：2013-08-13
申请号：US13455176
申请日：2012-04-25
申请人： Andres Bryant , Edward J. Nowak
发明人： Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/8224
CPC分类号： H01L21/845 , H01L21/84 , H01L27/1203 , H01L27/1211
摘要： Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.
摘要翻译：公开了具有集成电压均衡的具有串联的平面或非平面场效应晶体管（FET）的集成电路器件和形成器件的方法。串联连接的FET包括沿着半导体本体定位的门，以限定用于串联连接的FET的沟道区。源极/漏极区域位于沟道区域的相对侧上的半导体本体内，使得相邻栅极之间的半导体本体的每个部分包括用于一个场效应晶体管的一个源极/漏极区域，用于与另一个场效应晶体管的另一个源极/漏极区域相邻接。集成电压均衡通过具有期望电阻的并行导电层实现，并且位于串联连接的FET上，使得其与栅极电隔离，但与半导体本体内的源极/漏极区域接触。

12. 发明申请

US20130193481A1 FIELD EFFECT TRANSISTOR AND A METHOD OF FORMING THE TRANSISTOR 失效
标题翻译：场效应晶体管和形成晶体管的方法
公开(公告)号：US20130193481A1
公开(公告)日：2013-08-01
申请号：US13359615
申请日：2012-01-27
申请人： Andres Bryant , Edward J. Nowak
发明人： Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/66742 , H01L29/66795 , H01L29/785 , H01L29/78621 , H01L29/78684
摘要： Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region.
摘要翻译：公开了金属氧化物半导体场效应晶体管（MOSFET）结构的实施例和形成该结构的方法。该结构包括源极/漏极区域和源极/漏极区域之间的沟道区域。源极/漏极区域可以包括对源极/漏极掺杂剂具有高扩散性的硅。通道区域可以包括选择用于最佳电荷载流子迁移率和带能量以及其低源极/漏极掺杂剂扩散率的硅合金。在处理期间，源/漏掺杂剂可以扩散到沟道区的边缘部分。然而，由于硅合金对源极/漏极掺杂剂的低扩散性，掺杂剂不会深入沟道区域。因此，硅合金沟道区域的边缘部分可以具有与源极/漏极区域基本相同的掺杂剂分布，但是与硅合金沟道区域的中心部分不同的掺杂剂分布。

13. 发明授权

US08492820B2 Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit 有权
标题翻译：集成电路和采用集成工艺步骤形成集成电路的深沟槽隔离结构和深沟槽电容器结构的方法
公开(公告)号：US08492820B2
公开(公告)日：2013-07-23
申请号：US13406664
申请日：2012-02-28
申请人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
IPC分类号： H01L29/94
CPC分类号： H01L21/76224 , H01L27/10829 , H01L27/10867 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
摘要翻译：公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

14. 发明申请

US20130113050A1 BLANKET SHORT CHANNEL ROLL-UP IMPLANT WITH NON-ANGLED LONG CHANNEL COMPENSATING IMPLANT THROUGH PATTERNED OPENING 有权
公开(公告)号：US20130113050A1
公开(公告)日：2013-05-09
申请号：US13289051
申请日：2011-11-04
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1041 , H01L21/2652 , H01L21/26586 , H01L21/28026 , H01L29/0847 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/66583 , H01L29/6659 , H01L29/78
摘要： A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

15. 发明授权

US08420460B2 Method, structure and design structure for customizing history effects of SOI circuits 有权
公开(公告)号：US08420460B2
公开(公告)日：2013-04-16
申请号：US12055686
申请日：2008-03-26
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L29/78 , H01L29/42384 , H01L29/4908 , H01L29/512 , H01L29/7841
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.

16. 发明授权

US08383443B2 Non-uniform gate dielectric charge for pixel sensor cells and methods of manufacturing 有权
公开(公告)号：US08383443B2
公开(公告)日：2013-02-26
申请号：US12780193
申请日：2010-05-14
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L21/00
CPC分类号： H01L31/02 , H01L27/14614 , H01L27/14689
摘要： A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric.

17. 发明授权

US08343836B2 Recessed gate channel with low Vt corner 有权
标题翻译：嵌入门通道低Vt角
公开(公告)号：US08343836B2
公开(公告)日：2013-01-01
申请号：US13363944
申请日：2012-02-01
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/1083 , H01L29/4236 , H01L29/517 , H01L29/66621 , H01L29/78
摘要： A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region.
摘要翻译：凹陷栅极FET器件包括具有上部和下部的衬底，下部具有比上部更低的掺杂剂材料的浓度; 限定周围通道区域并且具有内衬的栅极电介质材料层的沟槽型栅电极，并且包括具有凹陷的顶表面的导电材料，以减少相对于在上基板表面处形成的源极和漏极扩散区域的重叠电容侧电极。在栅电极的任一侧和邻接栅电极处可选地形成卤素植入物，每个卤素注入物延伸到源极和漏极扩散到沟道区域之内。此外，形成高掺杂的源极和漏极延伸区域，其提供从源极和漏极扩散区域到沟道区域的低电阻路径。

18. 发明授权

US08237471B2 Circuit with stacked structure and use thereof 有权
标题翻译：具有堆叠结构的电路及其用途
公开(公告)号：US08237471B2
公开(公告)日：2012-08-07
申请号：US12626169
申请日：2009-11-25
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H03K19/20
CPC分类号： H03K19/20
摘要： An NAND circuit has a stacked structure having at least one symmetric NFET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET.
摘要翻译： NAND电路具有在堆叠的底部具有至少一个对称NFET的堆叠结构。更具体地，该电路具有堆叠结构，其包括不对称FET和对称FET。对称FET放置在层叠结构的底部，比不对称FET更接近地。

19. 发明申请

US20120153431A1 INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT 有权
标题翻译：集成电路和使用集成工艺步骤形成集成电路的深层隔离分离结构和深层电容电容器结构的方法
公开(公告)号：US20120153431A1
公开(公告)日：2012-06-21
申请号：US13406664
申请日：2012-02-28
申请人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
IPC分类号： H01L29/06
CPC分类号： H01L21/76224 , H01L27/10829 , H01L27/10867 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
摘要翻译：公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

20. 发明申请

US20120145650A1 NANO-FILTER AND METHOD OF FORMING SAME, AND METHOD OF FILTRATION 失效
标题翻译：纳滤器及其形成方法，以及过滤方法
公开(公告)号：US20120145650A1
公开(公告)日：2012-06-14
申请号：US12966370
申请日：2010-12-13
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
IPC分类号： B01D35/28 , B01D37/00 , B01D35/30 , B82Y5/00 , B82Y40/00
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译：本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。纳米线结构可以包括多个垂直堆叠的水平纳米线。

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