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11. 发明申请

US20050269622A1 Semiconductor memory array of floating gate memory cells with program/erase and select gates, and methods of making and operating same 有权
标题翻译：具有编程/擦除和选择栅极的浮动栅极存储器单元的半导体存储器阵列，以及制造和操作相同的方法
公开(公告)号：US20050269622A1
公开(公告)日：2005-12-08
申请号：US10863030
申请日：2004-06-07
申请人： Pavel Klinger , Amitay Levi
发明人： Pavel Klinger , Amitay Levi
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.
摘要翻译：存储器件及其制造和操作方法，包括第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，其间具有沟道区，导电浮置栅极具有设置在所述沟道区域上方并与所述沟道区域绝缘的第一部分和设置在所述第一区域上并与所述第一区域绝缘的第二部分，并且包括锐化边缘;导电P / E门，其具有设置在所述第一区域上方并与所述第一区域绝缘的第一部分，第二部分，其在浮动栅极第二部分上方和上方延伸并且通过第一绝缘材料层与其绝缘;以及导电选择栅极，其具有横向邻近所述浮动栅极设置并设置在所述沟道区域上并与所述沟道区域绝缘的第一部分。

12. 发明授权

US06878591B2 Self aligned method of forming non-volatile memory cells with flat word line 有权
标题翻译：形成具有平坦字线的非易失性存储单元的自对准方法
公开(公告)号：US06878591B2
公开(公告)日：2005-04-12
申请号：US10310441
申请日：2002-12-04
申请人： Pavel Klinger , Sreeni Maheshwarla
发明人： Pavel Klinger , Sreeni Maheshwarla
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A method of forming an electrically erasable non-volatile memory cell array. Each memory cell includes a floating gate, a block of insulation material over the floating gate, and a control gate disposed laterally adjacent to and over the floating gate. The insulation material block is formed with a planarized upper surface (using a dummy poly layer as a planarization etch stop). The control gate is formed with a planarized upper surface (using the insulation material block upper surface as a planarization etch stop).
摘要翻译：一种形成电可擦除非易失性存储单元阵列的方法。每个存储单元包括浮动栅极，浮置栅极上的绝缘材料块，以及横向邻近浮动栅极设置的控制栅极。绝缘材料块形成有平坦化的上表面（使用虚拟多晶硅层作为平坦化蚀刻停止）。控制栅极形成有平坦化的上表面（使用绝缘材料块上表面作为平坦化蚀刻停止）。

13. 发明授权

US06396737B2 High density flash memory architecture with columnar substrate coding 有权
标题翻译：具有柱状衬底编码的高密度闪存架构
公开(公告)号：US06396737B2
公开(公告)日：2002-05-28
申请号：US09733427
申请日：2000-12-08
申请人： Sukyoon Yoon , Pavel Klinger , Joo Young Yoon
发明人： Sukyoon Yoon , Pavel Klinger , Joo Young Yoon
IPC分类号： G11C1140
CPC分类号： H01L27/11521 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C2211/565 , H01L27/115
摘要： Instead of using a common substrate (101) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions (304) of the substrate (101), and independent access to each of these columnar regions (304) is provided. First, the independent access to each of these columnar regions (304) provides a capability for achieving more precise control over the voltage on the floating gates (106). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Second, the independent access to each of these columnar regions (304) also provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Finally, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region (304), no high voltages need to be applied to either the drain (102) or source (104). This is advantageous in that the minimum distance required by cell punchthrough is reduced. Hence, higher densities of flash memory may be achieved.
摘要翻译：代替对快闪存储器的每个扇区使用公共衬底（101），使用沟槽来隔离衬底（101）的柱状有源衬底区域（304），并且提供对这些柱状区域（304）中的每一个的独立访问。首先，对这些柱状区域（304）中的每一个的独立访问提供了实现对浮动栅极（106）上的电压的更精确控制的能力。例如，根据本发明的闪速存储器更适合于多级存储（每个单元存储超过1位的信息）。第二，对这些柱状区域（304）中的每一个的独立访问还提供了一次能够擦除小于整个扇区的闪存区域的能力。最后，由于通过来自柱状有源衬底区域（304）的冷电子隧穿来实现编程和擦除，所以不需要将高电压施加到漏极（102）或源极（104）。这是有利的，因为电池穿透所需的最小距离减小了。因此，可以实现更高密度的闪速存储器。

14. 发明授权

US06198658B1 High density flash memory architecture with columnar substrate coding 有权
标题翻译：具有柱状衬底编码的高密度闪存架构
公开(公告)号：US06198658B1
公开(公告)日：2001-03-06
申请号：US09415770
申请日：1999-10-08
申请人： Sukyoon Yoon , Pavel Klinger , Joo Young Yoon
发明人： Sukyoon Yoon , Pavel Klinger , Joo Young Yoon
IPC分类号： G11C1140
CPC分类号： H01L27/11521 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C2211/565 , H01L27/115
摘要： Instead of using a common substrate (101) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions (304) of the substrate (101), and independent access to each of these columnar regions (304) is provided. First, the independent access to each of these columnar regions (304) provides a capability for achieving more precise control over the voltage on the floating gates (106). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Second, the independent access to each of these columnar regions (304) also provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Finally, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region (304), no high voltages need to be applied to either the drain (102) or source (104). This is advantageous in that the minimum distance required by cell punchthrough is reduced. Hence, higher densities of flash memory may be achieved.
摘要翻译：代替对快闪存储器的每个扇区使用公共衬底（101），使用沟槽来隔离衬底（101）的柱状有源衬底区域（304），并且提供对这些柱状区域（304）中的每一个的独立访问。首先，对这些柱状区域（304）中的每一个的独立访问提供了实现对浮动栅极（106）上的电压的更精确控制的能力。例如，根据本发明的闪速存储器更适合于多级存储（每个单元存储超过1位的信息）。第二，对这些柱状区域（304）中的每一个的独立访问还提供了一次能够擦除小于整个扇区的闪存区域的能力。最后，由于通过来自柱状有源衬底区域（304）的冷电子隧穿来实现编程和擦除，所以不需要将高电压施加到漏极（102）或源极（104）。这是有利的，因为电池穿透所需的最小距离减小了。因此，可以实现更高密度的闪速存储器。

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