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11. 发明申请

US20060190733A1 Methods and apparatus for resource management in a processor 审中-公开
标题翻译：处理器中资源管理的方法和装置
公开(公告)号：US20060190733A1
公开(公告)日：2006-08-24
申请号：US11347618
申请日：2006-02-03
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： H04L9/00
CPC分类号： G06F21/53 , A63F13/12 , A63F13/71 , A63F2300/532 , A63F2300/5586 , G06F21/10 , G06F21/51 , G06Q20/123
摘要： Methods and apparatus provide for receiving encrypted content including program code, data, and a digital signature in a memory of a processing system, the content being encrypted using a first key; decrypting the encrypted content using a second key stored locally within the processing system; retrieving the digital signature from the content and verifying its authenticity; and permitting use of one or more processing resources that are operable to facilitate the execution of the program code by a processor of the processing system if the digital signature is authentic.
摘要翻译：方法和装置提供在处理系统的存储器中接收包括程序代码，数据和数字签名的加密内容，所述内容使用第一密钥加密; 使用在处理系统内本地存储的第二密钥对加密内容进行解密; 从内容中检索数字签名并验证其真实性; 并且如果数字签名是可信的，则允许使用一个或多个处理资源，所述处理资源可操作以便于处理系统的处理器执行程序代码。

12. 发明授权

US08185748B2 Methods and apparatus for facilitating a secure processor functional transition 有权
标题翻译：促进安全处理器功能转换的方法和装置
公开(公告)号：US08185748B2
公开(公告)日：2012-05-22
申请号：US11347067
申请日：2006-02-03
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： G06F21/00
CPC分类号： G06F21/51 , G06F21/57 , G06F21/575 , G06F21/74 , G06F2221/2105 , H04L9/3236 , H04L2209/60
摘要： A processor and associated local memory are capable of operative connection to a main memory such that data may be read from the main memory for use in the local memory, and the processor is operable to carry out actions, including: entering a secure mode of operation where externally initiated requests to read data from or write data into the processor are not serviced but internally initiated data transfers are serviced; reading a decryption program from a storage medium into the local memory of the processor; reading an encrypted authentication program into the local memory of the processor; decrypting the encrypted authentication program using a decryption program; and transitioning functionality of the processor from the decryption program to the authentication program.
摘要翻译：处理器和相关联的本地存储器能够与主存储器操作连接，使得可以从主存储器读取数据以在本地存储器中使用，并且处理器可操作以执行动作，包括：进入安全操作模式其中外部发起的从数据读取或将数据写入处理器的请求不被服务，但是内部启动的数据传输被服务; 从存储介质读取解密程序到所述处理器的本地存储器; 将加密认证程序读入处理器的本地存储器; 使用解密程序解密加密的认证程序; 以及将处理器从解密程序转换到认证程序的功能。

13. 发明授权

US08065526B2 Methods and apparatus for content control using processor resource management 有权
标题翻译：使用处理器资源管理的内容控制方法和装置
公开(公告)号：US08065526B2
公开(公告)日：2011-11-22
申请号：US11347068
申请日：2006-02-03
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： H04L29/00
CPC分类号： G06F21/10 , G06F2221/2107 , H04L9/3247 , H04L2209/60
摘要： Methods and apparatus provide for: requiring that a content provider seeking to have its content executed by a processing system enter into an accord with a processing system provider; receiving a second key and a digital signature from the content provider to the processing system provider, the second key being operable to decrypt the content when it has been encrypted with a first key, and the digital signature indicating that the accord has been reached; receiving the encrypted content from the content provider in a memory of the processing system; and preventing use of one or more processing resources of the processing system that are otherwise operable to facilitate the execution of the content unless the digital signature is received from the processing system provider.
摘要翻译：方法和装置提供：要求寻求使处理系统执行其内容的内容提供者与处理系统提供者一致; 从所述内容提供商接收第二密钥和数字签名到所述处理系统提供者，所述第二密钥可操作以在用第一密钥加密时对所述内容进行解密，并且所述数字签名指示已达到协议; 在所述处理系统的存储器中从所述内容提供商接收所述加密内容; 以及防止使用处理系统的一个或多个处理资源，除非从处理系统提供商接收到数字签名，否则处理系统的另外可操作以便于内容的执行。

14. 发明授权

US08001390B2 Methods and apparatus for secure programming and storage of data using a multiprocessor in a trusted mode 有权
标题翻译：用于在可信模式下使用多处理器进行数据安全编程和存储的方法和装置
公开(公告)号：US08001390B2
公开(公告)日：2011-08-16
申请号：US11746412
申请日：2007-05-09
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： G06F12/14 , G06F21/00 , G06F21/02 , G06F21/22
CPC分类号： G06F12/1416 , G06F12/0815 , G06F12/0862 , G06F12/0897 , G06F21/74
摘要： Methods and apparatus provide for: entering a secure mode in which a given processor may initiate a transfer of information into or out of said processor, but no external device may initiate a transfer of information into or out of said processor; and programming at least one trusted data storage location using a direct memory access (DMA) command to be one of read-only, write-only, readable and writeable, limited access, and reset, where said at least one trusted data storage location is located external to said processor.
摘要翻译：方法和装置提供：进入安全模式，其中给定处理器可以发起信息进入或离开所述处理器，但是没有外部设备可以发起信息传入或传出所述处理器; 以及使用直接存储器访问（DMA）命令将至少一个可信数据存储位置编程为只读，只写，可读和可写，有限访问和重置之一，其中所述至少一个可信数据存储位置是位于所述处理器外部。

15. 发明授权

US08001377B2 Methods and apparatus for secure data processing and transmission 有权
标题翻译：用于安全数据处理和传输的方法和装置
公开(公告)号：US08001377B2
公开(公告)日：2011-08-16
申请号：US12352817
申请日：2009-01-13
申请人： Masakazu Suzuoki , Akiyuki Hatakeyama
发明人： Masakazu Suzuoki , Akiyuki Hatakeyama
IPC分类号： H04L9/00
CPC分类号： G06F21/72 , G06F21/74
摘要： Methods and apparatus provide for placing an apparatus into at least one of a plurality of operational modes, wherein: the apparatus includes a local memory, a bus operable to carry information to and from the local memory, one or more arithmetic processing units operable to process data and operatively coupled to the local memory, and a security circuit operable to place the apparatus into the operational modes; and the plurality of operational modes includes: (i) a first mode whereby the apparatus and an external device are operable to initiate a transfer of information into or out of the memory over the bus, (ii) a second mode whereby neither the apparatus nor the external device are operable to initiate a transfer of information into or out of the memory over the bus, and (iii) a third mode whereby the apparatus is operable to initiate a transfer of information into or out of the local memory over the bus, but the external device is not operable to initiate a transfer of information into or out of the local memory over the bus.
摘要翻译：方法和装置提供将装置放置在多种操作模式中的至少一种中，其中：所述装置包括本地存储器，可操作以向本地存储器携带信息的总线，可操作以处理的一个或多个算术处理单元数据并且可操作地耦合到本地存储器，以及可操作以将设备置于操作模式的安全电路; 并且所述多个操作模式包括：（i）第一模式，其中所述设备和外部设备可操作以通过总线发起信息传入或传出所述存储器;（ii）第二模式，外部设备可操作以通过总线启动信息传入或传出存储器，以及（iii）第三模式，其中该设备可操作以通过总线启动信息传入或传出本地存储器，但是外部设备不可操作以通过总线发起信息传入或传出本地存储器。

16. 发明申请

US20090313456A1 METHODS AND APPARATUS FOR DYNAMIC PREDICTION BY SOFTWARE 有权
标题翻译：软件动态预测的方法和装置
公开(公告)号：US20090313456A1
公开(公告)日：2009-12-17
申请号：US12540522
申请日：2009-08-13
申请人： Masahiro Yasue , Akiyuki Hatakeyama
发明人： Masahiro Yasue , Akiyuki Hatakeyama
IPC分类号： G06F9/38
CPC分类号： G06F9/3846 , G06F9/30047 , G06F9/30072 , G06F9/3804
摘要： A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.
摘要翻译：一种用于指定与用于实现分支操作的分支指令相关联的条件预取指令的第一部分中的值的方法，存储介质，处理器指令和处理器，在指令的第二部分中指定目标指令地址提供该值，以确定是否满足条件，并且在满足条件时将从目标指令地址开始的一个或多个指令预取到处理器的指令缓冲器中。

17. 发明申请

US20070240013A1 Methods And Apparatus For Managing Defective Processors Through Clock Programming 审中-公开
标题翻译：通过时钟编程管理不良处理器的方法和装置
公开(公告)号：US20070240013A1
公开(公告)日：2007-10-11
申请号：US11620877
申请日：2007-01-08
申请人： Atsushi Hayashi , Akiyuki Hatakeyama , Taichi Niki , Yoichi Nishino
发明人： Atsushi Hayashi , Akiyuki Hatakeyama , Taichi Niki , Yoichi Nishino
IPC分类号： G06F1/00
CPC分类号： G06F1/10 , G06F11/2043 , G06F11/24
摘要： An apparatus is disclosed which may include a plurality of circuit blocks, each circuit block including a separate clock grid; at least one oscillator circuit operable to select frequencies for at least two respective clock signals and to transmit the at least two clock signals to respective ones of said plurality of circuit blocks; and a control circuit coupled to the at least one oscillator circuit.
摘要翻译：公开了一种可以包括多个电路块的装置，每个电路块包括单独的时钟网格; 至少一个振荡器电路，可操作以选择至少两个相应时钟信号的频率，并将所述至少两个时钟信号发送到所述多个电路块中的相应电路块; 以及耦合到所述至少一个振荡器电路的控制电路。

18. 发明申请

US20070180249A1 Methods and apparatus for content control using processor resource management 有权
标题翻译：使用处理器资源管理的内容控制方法和装置
公开(公告)号：US20070180249A1
公开(公告)日：2007-08-02
申请号：US11347068
申请日：2006-02-03
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： H04L9/00
CPC分类号： G06F21/10 , G06F2221/2107 , H04L9/3247 , H04L2209/60
摘要： Methods and apparatus provide for: requiring that a content provider seeking to have its content executed by a processing system enter into an accord with a processing system provider; receiving a second key and a digital signature from the content provider to the processing system provider, the second key being operable to decrypt the content when it has been encrypted with a first key, and the digital signature indicating that the accord has been reached; receiving the encrypted content from the content provider in a memory of the processing system; and preventing use of one or more processing resources of the processing system that are otherwise operable to facilitate the execution of the content unless the digital signature is received from the processing system provider.
摘要翻译：方法和装置提供：要求寻求使处理系统执行其内容的内容提供者与处理系统提供者一致; 从所述内容提供商接收第二密钥和数字签名到所述处理系统提供者，所述第二密钥可操作以在用第一密钥加密时对所述内容进行解密，并且所述数字签名指示已达到协议; 在所述处理系统的存储器中从所述内容提供商接收所述加密内容; 以及防止使用处理系统的一个或多个处理资源，除非从处理系统提供商接收到数字签名，否则处理系统的另外可操作以便于内容的执行。

19. 发明申请

US20060179487A1 Methods and apparatus for secure processor collaboration in a multi-processor system 有权
标题翻译：用于在多处理器系统中进行安全处理器协作的方法和装置
公开(公告)号：US20060179487A1
公开(公告)日：2006-08-10
申请号：US11346946
申请日：2006-02-03
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： H04N7/16 , H04L9/32 , G06F17/30 , G06F7/04 , G06K9/00 , H03M1/68 , H04K1/00 , H04L9/00
CPC分类号： G06F21/6209 , G06F12/1458 , G06F21/53 , G06F21/575 , G06F21/71 , G06F21/79
摘要： In a multi-processor system including a plurality of processors capable of being operatively coupled to the main memory and each processor including an associated local memory, and at least one main processor operable to control access by the processors to data within the main memory and within the processors, methods and apparatus provide for: entering a secure mode of operation within at least one of the processors in which no requests initiated by others of the processors for data transfers into or out of the at least one processor are serviced, but such transfers initiated by the at least one processor are serviced subject to the access controlled by the main processing unit; and using the main processing unit to exclude access to data associated with at least one further processor by others of the processors except for the at least one processor.
摘要翻译：在包括能够可操作地耦合到主存储器并且每个处理器包括相关本地存储器的多个处理器的多处理器系统中，以及至少一个主处理器，其可操作以控制处理器对主存储器内的数据的访问，处理器，方法和装置提供：在至少一个处理器内进入安全操作模式，其中由处理器中的其他处理器发起的用于数据传送到或移出至少一个处理器的请求被服务，但这样的传送由所述至少一个处理器发起的服务受到由主处理单元控制的访问; 以及使用所述主处理单元排除除了所述至少一个处理器之外的所述处理器中的其他处理器与至少一个另外的处理器相关联的数据的访问。

20. 发明授权

US08726041B2 Methods and apparatus for generating a random number in one or more isolated processors 有权
标题翻译：用于在一个或多个隔离处理器中生成随机数的方法和装置
公开(公告)号：US08726041B2
公开(公告)日：2014-05-13
申请号：US11746423
申请日：2007-05-09
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： G06F21/00
CPC分类号： G06F7/58 , G06F21/74 , H04L9/0662 , H04L2209/125
摘要： A system and method is disclosed which may include providing at least one processor with an integrally disposed random number generator (RNG) therein; entering a protected mode by said at least one processor; and generating a random number using said RNG in said at least one processor after entering said protected mode.
摘要翻译：公开了一种系统和方法，其可以包括：提供至少一个处理器，其中具有整体设置的随机数发生器（RNG）; 通过所述至少一个处理器进入保护模式; 以及在进入所述保护模式之后，在所述至少一个处理器中使用所述RNG生成随机数。

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