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11. 发明授权

US10929944B2 Low power and low latency GPU coprocessor for persistent computing 有权
公开(公告)号：US10929944B2
公开(公告)日：2021-02-23
申请号：US15360057
申请日：2016-11-23
申请人： Advanced Micro Devices, Inc.
发明人： Jiasheng Chen , Timour Paltashev , Alexander Lyashevsky , Carl Kittredge Wakeland , Michael J. Mantor
IPC分类号： G06T1/20 , G06F9/54 , G06F9/38 , G06T1/60
摘要： Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

12. 发明申请

US20180144435A1 LOW POWER AND LOW LATENCY GPU COPROCESSOR FOR PERSISTENT COMPUTING 审中-公开
公开(公告)号：US20180144435A1
公开(公告)日：2018-05-24
申请号：US15360057
申请日：2016-11-23
申请人： Advanced Micro Devices, Inc.
发明人： Jiasheng Chen , Timour Paltashev , Alexander Lyashevsky , Carl Kittredge Wakeland , Michael J. Mantor
IPC分类号： G06T1/20 , G06T1/60
CPC分类号： G06T1/20 , G06F9/3887 , G06F9/542 , G06F2009/3883 , G06F2209/548 , G06T1/60
摘要： Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

13. 发明申请

US20150332427A1 REDUNDANCY METHOD AND APPARATUS FOR SHADER COLUMN REPAIR 审中-公开
标题翻译：冗余方法和设备用于阴影柱修复
公开(公告)号：US20150332427A1
公开(公告)日：2015-11-19
申请号：US14808113
申请日：2015-07-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Michael J. Mantor , Jeffrey T. Brady , Angel E. Socarras
IPC分类号： G06T1/20 , G06T1/60
CPC分类号： G06T1/20 , G06T1/60 , G09G5/363 , G09G2360/06
摘要： Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. The shader pipe array includes multiple shader pipes, each of which perform rendering calculations on data provided thereto. The redundant shader pipe array also performs rendering calculations on data provided thereto. The sequencer identifies at least one defective shader pipe in the shader pipe array, and, in response, generates a signal. The redundant shader switch receives the generated signal, and, in response, transfers the data destined for each shader pipe identified as being defective independently to the redundant shader pipe array.
摘要翻译：描述了方法，系统和非暂时性计算机可读介质。系统包括着色器管道阵列，冗余着色器管道阵列，定序器和冗余着色器开关。着色器管道阵列包括多个着色器管道，每个管道对其提供的数据执行渲染计算。冗余着色器管道阵列还对提供给它的数据执行渲染计算。定序器在着色器管道阵列中识别至少一个有缺陷的着色器管道，并作为响应生成信号。冗余着色器开关接收所生成的信号，并作为响应，将指定为每个着色器管道的数据独立地传输到冗余着色器管道阵列。

14. 发明申请

US20230055695A1 VMID AS A GPU TASK CONTAINER FOR VIRTUALIZATION 有权
公开(公告)号：US20230055695A1
公开(公告)日：2023-02-23
申请号：US18045128
申请日：2022-10-07
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Anirudh R. Acharya , Michael J. Mantor , Rex Eldon McCrary , Anthony Asaro , Jeffrey Gongxian Cheng , Mark Fowler
IPC分类号： G06F9/48 , G06F9/52 , G06F9/54 , G06F12/1009 , G06F12/14 , G06T1/20
摘要： Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

15. 发明申请

US20210011760A1 VMID AS A GPU TASK CONTAINER FOR VIRTUALIZATION 有权
公开(公告)号：US20210011760A1
公开(公告)日：2021-01-14
申请号：US16938381
申请日：2020-07-24
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Anirudh R. Acharya , Michael J. Mantor , Rex Eldon McCrary , Anthony Asaro , Jeffrey Gongxian Cheng , Mark Fowler
IPC分类号： G06F9/48 , G06F9/52 , G06F9/54 , G06F12/1009 , G06F12/14 , G06T1/20
摘要： Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

16. 发明授权

US10474468B2 Indicating instruction scheduling mode for processing wavefront portions 有权
公开(公告)号：US10474468B2
公开(公告)日：2019-11-12
申请号：US15439540
申请日：2017-02-22
申请人： Advanced Micro Devices, Inc.
发明人： Michael J. Mantor , Brian D. Emberling , Mark Fowler , Mark M. Leather
IPC分类号： G06F9/38 , G06T1/20 , G06F9/30
摘要： Systems, apparatuses, and methods for processing variable wavefront sizes on a processor are disclosed. In one embodiment, a processor includes at least a scheduler, cache, and multiple execution units. When operating in a first mode, the processor executes the same instruction on multiple portions of a wavefront before proceeding to the next instruction of the shader program. When operating in a second mode, the processor executes a set of instructions on a first portion of a wavefront. In the second mode, when the processor finishes executing the set of instructions on the first portion of the wavefront, the processor executes the set of instructions on a second portion of the wavefront, and so on until all portions of the wavefront have been processed. The processor determines the operating mode based on one or more conditions.

17. 发明申请

US20190004807A1 STREAM PROCESSOR WITH OVERLAPPING EXECUTION 审中-公开
公开(公告)号：US20190004807A1
公开(公告)日：2019-01-03
申请号：US15657478
申请日：2017-07-24
申请人： Advanced Micro Devices, Inc.
发明人： Jiasheng Chen , Qingcheng Wang , Yunxiao Zou , Bin He , Jian Yang , Michael J. Mantor , Brian D. Emberling
IPC分类号： G06F9/38
摘要： Systems, apparatuses, and methods for implementing a stream processor with overlapping execution are disclosed. In one embodiment, a system includes at least a parallel processing unit with a plurality of execution pipelines. The processing throughput of the parallel processing unit is increased by overlapping execution of multi-pass instructions with single pass instructions without increasing the instruction issue rate. A first plurality of operands of a first vector instruction are read from a shared vector register file in a single clock cycle and stored in temporary storage. The first plurality of operands are accessed and utilized to initiate multiple instructions on individual vector elements on a first execution pipeline in subsequent clock cycles. A second plurality of operands are read from the shared vector register file during the subsequent clock cycles to initiate execution of one or more second vector instructions on the second execution pipeline.

18. 发明授权

US10152434B2 Efficient arbitration for memory accesses 有权
公开(公告)号：US10152434B2
公开(公告)日：2018-12-11
申请号：US15385566
申请日：2016-12-20
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Rostyslav Kyrychynskyi , Anthony Asaro , Kostantinos Danny Christidis , Mark Fowler , Michael J. Mantor , Robert Scott Hartog
IPC分类号： G06F13/14 , G06F13/16 , G06F13/36 , G06F13/40
摘要： A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.

19. 发明申请

US20180239635A1 SUSPEND AND RESTORE PROCESSOR OPERATIONS 审中-公开
公开(公告)号：US20180239635A1
公开(公告)日：2018-08-23
申请号：US15438466
申请日：2017-02-21
申请人： Advanced Micro Devices, Inc.
发明人： Alexander Fuad Ashkar , Michael J. Mantor , Randy Wayne Ramsey , Rex Eldon McCrary , Harry J. Wise
IPC分类号： G06F9/48
摘要： Systems, apparatuses, and methods for suspending and restoring operations on a processor are disclosed. In one embodiment, a processor includes at least a control unit, multiple execution units, and multiple work creation units. In response to detecting a request to suspend a software application executing on the processor, the control unit sends requests to the plurality of work creation units to stop creating new work. The control unit waits until receiving acknowledgements from the work creation units prior to initiating a suspend operation. Once all work creation units have acknowledged that they have stopped creating new work, the control unit initiates the suspend operation. Also, when a restore operation is initiated, the control unit prevents any work creation units from launching new work-items until all previously in-flight work-items have been restored to the same work creation units and execution units to which they were previously allocated.

20. 发明申请

US20180210657A1 SOFTWARE CONTROL OF STATE SETS 审中-公开
公开(公告)号：US20180210657A1
公开(公告)日：2018-07-26
申请号：US15417011
申请日：2017-01-26
申请人： Advanced Micro Devices, Inc.
发明人： Rex Eldon McCrary , Michael J. Mantor , Alexander Fuad Ashkar , Harry J. Wise
IPC分类号： G06F3/06 , G06F9/48
CPC分类号： G06F3/0607 , G06F3/0619 , G06F3/0634 , G06F3/065 , G06F3/067 , G06F9/4881 , G06F9/50
摘要： Systems, apparatuses, and methods for implementing software control of state sets are disclosed. In one embodiment, a processor includes at least an execution unit and a plurality of state registers. The processor is configured to detect a command to allocate a first state set for storing a first state, wherein the command is generated by software, and wherein the first state specifies values for the plurality of state registers. The command is executed on the execution unit while the processor is in a second state, wherein the second state is different from the first state. The first state set of the processor is allocated with the first state responsive to executing the command on the execution unit. The processor is configured to allocate the first state set for the first state prior to the processor entering the first state.

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