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11. 发明授权

US07664172B1 Receiver system having analog pre-filter and digital equalizer 有权
标题翻译：接收机系统具有模拟预滤波器和数字均衡器
公开(公告)号：US07664172B1
公开(公告)日：2010-02-16
申请号：US11505137
申请日：2006-08-15
申请人： Tulsi Manickam , Peter J. Sallaway , Sreen A. Raghavan , Abhijit M. Phanse , James B. Wieser
发明人： Tulsi Manickam , Peter J. Sallaway , Sreen A. Raghavan , Abhijit M. Phanse , James B. Wieser
IPC分类号： H03H7/30 , H04B1/10 , H04L1/00
CPC分类号： H04L25/03057 , H04L25/03254
摘要： A receiver system contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605) arranged sequentially for processing an input analog signal (yk). The pre-filter produces a filtered analog signal (Zs) with reduced intersymbol interference. The converter provides analog-to-digital signal conversion. Digital equalization circuitry in the equalizer operates according to a transfer frmnction c - 1 ⁢ z + c 0 + ∑ M i = 1 ⁢ c i ⁢ z - i to produce an equalized digital signal (a'k) as a stream of equalized digital values. Coefficients c−1 and c0 are fixed. Each other coefficient ci is adaptively chosen. The decoder converts the equalized digital values, or intermediate values generated therefrom, into a stream of symbols. A receiver system may include two or more receivers each configured in the foregoing way with the digital equalization circuitry in each receiver operating according to a transfer function ∑ i = - N M ⁢ c i ⁢ z - i where at least coefficients c−1, c0, and c1 are non-zero.
摘要翻译：一个接收机系统包括一个模拟预滤波器（207或619），一个模数转换器（210），一个数字均衡器（212）和一个解码器（605），它们依次排列，用于处理输入的模拟信号（yk）。预滤波器产生具有减少的符号间干扰的滤波模拟信号（Zs）。该转换器提供模数转换。均衡器中的数字均衡电路根据传输速率c-1 z + c 0 +ΣM i = 1 ci z-i进行操作，以产生均衡数字信号（a'k）作为均衡数字值流。系数c-1和c0是固定的。自适应地选择其他系数ci。解码器将均衡的数字值或由其生成的中间值转换成符号流。接收机系统可以包括两个或更多个接收机，每个接收机以前述方式配置，其中每个接收机中的数字均衡电路根据传递函数Σi = - NM ci z-i进行操作，其中至少系数c-1，c0，而c1不为零。

12. 发明授权

US07646807B1 Receiver system with interdependent adaptive analog and digital signal equalization 有权
标题翻译：具有相互依赖的自适应模拟和数字信号均衡的接收机系统
公开(公告)号：US07646807B1
公开(公告)日：2010-01-12
申请号：US11490437
申请日：2006-07-19
申请人： Tulsi Manickam , Peter J. Sallaway , Sreen A. Raghavan , Abhijit M. Phanse , James B. Wieser
发明人： Tulsi Manickam , Peter J. Sallaway , Sreen A. Raghavan , Abhijit M. Phanse , James B. Wieser
IPC分类号： H04B1/10 , H04L1/00
CPC分类号： H04L25/03057 , H04L25/03254
摘要： An analog equalizer (613 and 614) adaptively equalizes an input analog signal affected with intersymbol interference (“ISI”), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter (210) converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer (212) adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder (605) decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols. Equalization control circuitry (213, 214, and 217) adjusts equalization filter characteristics of the equalizers such that adjustments of the filter characteristics of the analog equalizer depend adaptively on adaptive adjustments of the filter characteristics of the digital equalizer.
摘要翻译：模拟均衡器（613和614）自适应地使受到符号间干扰（“ISI”）影响的输入模拟信号或由其产生的中间模拟信号进行均衡，以产生具有减少的ISI的滤波的部分均衡的模拟信号。模数转换器（210）将经滤波的模拟信号或由其产生的中间模拟信号转换为初始数字信号。数字均衡器（212）自适应地均衡初始数字信号或由其产生的中间数字信号，以产生均衡数字信号作为具有进一步减小的ISI的均衡数字值流。输出解码器（605）将均衡的数字值或由其生成的中间数字值解码成符号流。均衡控制电路（213,214和217）调整均衡器的均衡滤波器特性，使得模拟均衡器的滤波器特性的调整自适应地依赖于数字均衡器的滤波器特性的自适应调整。

13. 发明授权

US07065133B1 Receiver architecture using mixed analog and digital signal processing and method of operation 有权
标题翻译：接收机架构采用混合模拟和数字信号处理及操作方法
公开(公告)号：US07065133B1
公开(公告)日：2006-06-20
申请号：US10878966
申请日：2004-06-28
申请人： Abhijit M. Phanse , Peter J. Sallaway , James B. Wieser
发明人： Abhijit M. Phanse , Peter J. Sallaway , James B. Wieser
IPC分类号： H04B1/38 , H03H7/30
CPC分类号： H04L25/45 , H04B3/23
摘要： There is disclosed a transceiver for use in a high speed Ethernet local area network (LAN). The transceiver comprises: 1) front-end analog signal processing circuitry comprising: a) a line driver for transmitting an outgoing analog signal to an external cable; b) a DC offset correction circuit for reducing a DC component in an incoming analog signal; c) an echo canceller; d) an automatic gain control (AGC) circuit; and e) an adaptive analog equalization filter. The transceiver also comprises: 2) an analog-to-digital converter (ADC) for converting the analog filter incoming signal to a first incoming digital signal; and 3) digital signal processing circuitry comprising: a) a digital finite impulse response (FIR) filter; b) a digital echo cancellation circuit to produce a reduced-echo incoming digital signal; c) a digital automatic gain control (AGC) circuit; and d) a digital base line wander circuit.
摘要翻译：公开了一种用于高速以太网局域网（LAN）的收发器。收发器包括：1）前端模拟信号处理电路，包括：a）线路驱动器，用于将输出的模拟信号发送到外部电缆; b）用于减少输入模拟信号中的DC分量的DC偏移校正电路; c）回声消除器; d）自动增益控制（AGC）电路; 和e）自适应模拟均衡滤波器。收发器还包括：2）用于将模拟滤波器输入信号转换为第一输入数字信号的模数转换器（ADC）; 以及3）数字信号处理电路，包括：a）数字有限脉冲响应（FIR）滤波器; b）数字回声消除电路，用于产生减少回波的数字信号; c）数字自动增益控制（AGC）电路; 和d）数字基线漂移电路。

14. 发明授权

US06975674B1 System and method for mixed mode equalization of signals 有权
标题翻译：信号混合模式均衡的系统和方法
公开(公告)号：US06975674B1
公开(公告)日：2005-12-13
申请号：US09570331
申请日：2000-05-12
申请人： Abhijit M. Phanse , Peter J. Sallaway , Thulasinath G. Manickam
发明人： Abhijit M. Phanse , Peter J. Sallaway , Thulasinath G. Manickam
IPC分类号： H04L5/16 , H04L25/03
CPC分类号： H04L25/03019
摘要： There is disclosed a mixed mode equalization system for use in a transceiver capable of operating in a high frequency Ethernet local area network (LAN). The mixed mode equalization system comprises: 1) an adaptive analog equalization filter for amplifying a first high frequency component of an incoming analog signal by a first adjustable gain factor to produce an analog filtered incoming signal; 2) an analog-to-digital converter (ADC) for converting the analog filter incoming signal to a first incoming digital signal; 3) a digital finite impulse response (FIR) filter for amplifying a second high frequency component of the first incoming digital signal factor to produce a digital filtered incoming signal; 4) a digital FIR controller for modifying at least one digital filter coefficient of the digital FIR filter according to a signal error associated with a digital output of the digital FIR filter; and 5) an analog equalization controller for modifying the first adjustable gain factor associated with the adaptive analog equalization filter according to a value of the at least one digital filter coefficient.
摘要翻译：公开了一种在能够在高频以太网局域网（LAN）中操作的收发器中使用的混合模式均衡系统。混合模式均衡系统包括：1）自适应模拟均衡滤波器，用于通过第一可调增益因子放大输入模拟信号的第一高频分量，以产生模拟滤波输入信号; 2）用于将模拟滤波器输入信号转换为第一输入数字信号的模数转换器（ADC）; 3）数字有限脉冲响应（FIR）滤波器，用于放大第一输入数字信号因子的第二高频分量以产生数字滤波输入信号; 4）数字FIR控制器，用于根据与数字FIR滤波器的数字输出相关联的信号误差来修改数字FIR滤波器的至少一个数字滤波器系数; 以及5）模拟均衡控制器，用于根据所述至少一个数字滤波器系数的值修改与所述自适应模拟均衡滤波器相关联的第一可调增益因子。

15. 发明申请

US20120183025A1 Optimal signal processing for twisted pair transceivers 有权
标题翻译：双绞线收发器的最佳信号处理
公开(公告)号：US20120183025A1
公开(公告)日：2012-07-19
申请号：US12319985
申请日：2009-01-12
申请人： Tulsi Manickam , Peter J. Sallaway , Sreen A. Raghavan , Abhijit M. Phanse , James B. Wieser
发明人： Tulsi Manickam , Peter J. Sallaway , Sreen A. Raghavan , Abhijit M. Phanse , James B. Wieser
IPC分类号： H04B1/38
CPC分类号： H04L25/03057 , H04L25/03254
摘要： A receiver that easily receives signals from transmission channels having long cable lengths is presented. The receiver includes an analog pre-filter that removes distortions and intersymbol interference from a predetermined transmission channel. The analog pre-filter is coupled with a digital receiver that provides digital equalization. The combination of analog equalization with digital equalization allows for simplified digital equalization while retaining the versatility of digital signal processing.
摘要翻译：提出了一种容易从具有长电缆长度的传输通道接收信号的接收机。接收机包括一个模拟预滤波器，用于消除来自预定传输信道的失真和符号间干扰。模拟预滤波器与提供数字均衡的数字接收机耦合。模拟均衡与数字均衡的组合允许简化的数字均衡，同时保持数字信号处理的通用性。

16. 发明授权

US08005135B1 Receiver system with interdependent adaptive analog and digital signal equalization 有权
标题翻译：具有相互依赖的自适应模拟和数字信号均衡的接收机系统
公开(公告)号：US08005135B1
公开(公告)日：2011-08-23
申请号：US12643965
申请日：2009-12-21
申请人： Tulsi Manickam , Peter J. Sallaway , Sreen A. Raghavan , Abhijit M. Phanse , James B. Wieser
发明人： Tulsi Manickam , Peter J. Sallaway , Sreen A. Raghavan , Abhijit M. Phanse , James B. Wieser
IPC分类号： H04B1/10 , H04L1/00
CPC分类号： H04L25/03057 , H04L25/03254
摘要： An analog equalizer (613 and 614) adaptively equalizes an input analog signal affected with intersymbol interference (“ISI”), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter (210) converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer (212) adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder (605) decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols. Equalization control circuitry (213, 214, and 217) adjusts equalization filter characteristics of the equalizers such that adjustments of the filter characteristics of one of the equalizers depend adaptively on adaptive adjustments of the filter characteristics of the other equalizer.
摘要翻译：模拟均衡器（613和614）自适应地使受到符号间干扰（“ISI”）影响的输入模拟信号或由其产生的中间模拟信号进行均衡，以产生具有减少的ISI的滤波的部分均衡的模拟信号。模数转换器（210）将经滤波的模拟信号或由其产生的中间模拟信号转换为初始数字信号。数字均衡器（212）自适应地均衡初始数字信号或由其产生的中间数字信号，以产生均衡数字信号作为具有进一步减小的ISI的均衡数字值流。输出解码器（605）将均衡的数字值或由其生成的中间数字值解码成符号流。均衡控制电路（213,214和217）调整均衡器的均衡滤波器特性，使得均衡器之一的滤波器特性的调整自适应地依赖于另一个均衡器的滤波器特性的自适应调整。

17. 发明授权

US06373338B1 Differential current mirror system and methods 有权
标题翻译：差分电流镜系统及方法
公开(公告)号：US06373338B1
公开(公告)日：2002-04-16
申请号：US09569958
申请日：2000-05-12
申请人： Abhijit M. Phanse , Michael X. Maida
发明人： Abhijit M. Phanse , Michael X. Maida
IPC分类号： H03F345
CPC分类号： H03F3/45183 , H03F2203/45344 , H03F2203/45544
摘要： There is disclosed a differential current mirror system and method for providing differential output current signals that are proportional to differential input current signals in which common mode current signals are rejected. The system comprises a pair of diode connected transistors and a differential amplifier. The pair of diode connected transistors comprises a first and second transistor coupled together. The differential amplifier comprises a third and fourth transistor coupled together in a differential amplifier configuration. The gate of the third transistor receives a first input current signal from the drain of the first transistor and the gate of the fourth transistor receives a second input current signal from the drain of the second transistor.
摘要翻译：公开了一种差分电流镜系统和方法，用于提供差分输出电流信号，其中差分输入电流信号与共模电流信号被拒绝。该系统包括一对二极管连接的晶体管和差分放大器。一对二极管连接的晶体管包括耦合在一起的第一和第二晶体管。差分放大器包括以差分放大器配置耦合在一起的第三和第四晶体管。第三晶体管的栅极接收来自第一晶体管的漏极的第一输入电流信号，第四晶体管的栅极从第二晶体管的漏极接收第二输入电流信号。

18. 发明授权

US06359511B1 System and method for current splitting for variable gain control 有权
标题翻译：用于可变增益控制的电流分配的系统和方法
公开(公告)号：US06359511B1
公开(公告)日：2002-03-19
申请号：US09570082
申请日：2000-05-12
申请人： Abhijit M. Phanse , Michael X. Maida
发明人： Abhijit M. Phanse , Michael X. Maida
IPC分类号： H03F345
CPC分类号： H03F3/345 , H03F1/301 , H03F3/45713 , H03F2200/456 , H03G1/00
摘要： There is disclosed a system and method for current splitting for variable gain control. The system comprises a current splitting circuit that splits an input current into a first current portion that is proportional to a first scale factor that has a value between zero and one. The remainder of the current is a second current portion that is proportional to a second scale factor that has a value that is equal to one minus the first scale factor. The current splitting circuit comprises a differential current mirror circuit that rejects common mode input current signals.
摘要翻译：公开了用于可变增益控制的电流分配的系统和方法。该系统包括电流分流电路，其将输入电流分成与第一比例因子成比例的第一电流部分，该第一比例因子具有在零和一之间的值。电流的剩余部分是与具有等于1的值减去第一比例因子的第二比例因子成比例的第二电流部分。电流分流电路包括抑制共模输入电流信号的差分电流镜电路。

19. 发明授权

US07254198B1 Receiver system having analog pre-filter and digital equalizer 有权
标题翻译：接收机系统具有模拟预滤波器和数字均衡器
公开(公告)号：US07254198B1
公开(公告)日：2007-08-07
申请号：US09561086
申请日：2000-04-28
申请人： Tulsi Manickam , Peter J. Sallaway , Sreen A. Raghavan , Abhijit M. Phanse , James B. Wieser
发明人： Tulsi Manickam , Peter J. Sallaway , Sreen A. Raghavan , Abhijit M. Phanse , James B. Wieser
IPC分类号： H04B1/10
CPC分类号： H04L25/03057 , H04L25/03254
摘要： A receiver system suitable for a local area network contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605). A symbol-information-carrying input analog signal (yk), or a first intermediate analog signal generated from the input analog signal, is filtered by filtering circuitry in the pre-filter to produce a filtered analog signal (Zs) with reduced intersymbol interference. The filtering circuitry operates according to a transfer function such as (b1s+1)/(a2s2+a1s+1) or (1−Vc)+VcPF(s) where Vc is adaptively varied. The analog-to-digital converter provides analog-to-digital signal conversion. The equalizer provides digital signal equalization to produce an equalized digital signal (a′k) as a stream of equalized digital values. The decoder converts the equalized digital values, or intermediate digital values generated from the equalized digital values, into a stream of symbols.
摘要翻译：适用于局域网的接收机系统包含模拟预滤波器（207或619），模拟 - 数字转换器（210），数字均衡器（212）和解码器（605）。由输入的模拟信号产生的符号信息输入模拟信号（或从输入的模拟信号产生的第一中间模拟信号）由预滤波器中的滤波电路进行滤波，以产生经滤波的模拟信号（Z s S）具有减少的符号间干扰。滤波电路根据传递函数进行操作，例如（b 1> 1 + 1）/（a 2＆lt; 2＆gt; 2＆lt; 1 + 1）或（1-V C c）+ V C c C（s）其中V C c C被自适应地变化。模数转换器提供模数转换。均衡器提供数字信号均衡以产生均衡的数字信号（一个“k”）作为均衡数字值的流。解码器将均衡的数字值或从均衡的数字值生成的中间数字值转换成符号流。

20. 发明授权

US07139342B1 System and method for cancelling signal echoes in a full-duplex transceiver front end 有权
标题翻译：用于在全双工收发器前端消除信号回波的系统和方法
公开(公告)号：US07139342B1
公开(公告)日：2006-11-21
申请号：US09569957
申请日：2000-05-12
申请人： Abhijit M. Phanse
发明人： Abhijit M. Phanse
IPC分类号： H04B1/10
CPC分类号： H04B3/23
摘要： There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor. The values of resistance and capacitance in the echo canceller impedance model circuit are varied in response to control signals from a echo canceller control circuit to compensate for and cancel signal echoes.
摘要翻译：公开了一种用于全双工收发器的回波消除器电路，其包括能够通过电缆发送模拟发射信号的线路驱动器并且包括能够从电缆接收模拟接收信号的线路接收器的线路接收机。回波消除器阻抗模型电路耦合到线路驱动器的输出端并耦合到线路接收机的输入。回波消除器阻抗模型电路产生质量相等并且与表示模拟接收信号中存在的信号回波的电流相位相反的回波消除器电流。回波消除器阻抗模型电路具有用于产生回波消除器电流的可变阻抗。可变阻抗具有至少一个可变电阻器和至少一个可变电容器。回波消除器阻抗模型电路中的电阻和电容值响应于来自回波消除器控制电路的控制信号而变化，以补偿和消除信号回波。

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