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11. 发明授权

US08501593B2 Method of NiSiGe epitaxial growth by introducing Al interlayer 失效
标题翻译：通过引入Al中间层的NiSiGe外延生长方法
公开(公告)号：US08501593B2
公开(公告)日：2013-08-06
申请号：US13260757
申请日：2011-07-25
申请人： Miao Zhang , Bo Zhang , Zhongying Xue , Xi Wang
发明人： Miao Zhang , Bo Zhang , Zhongying Xue , Xi Wang
IPC分类号： H01L27/092
CPC分类号： C30B29/52 , C30B1/00 , H01L21/28518 , H01L29/165 , H01L29/456
摘要： The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance.
摘要翻译：本发明公开了一种通过引入Al中间层的NiSiGe外延生长方法，包括在SiGe层的表面上沉积Al薄膜，随后在Al薄膜上沉积Ni层，然后在Ni之间进行退火处理 SiGe层的SiGe材料，形成NiSiGe材料。由于Al中间层的阻挡效应，NiSiGe层具有单晶结构，与SiGe衬底的平坦界面，厚度可达0.3nm，显着提高了界面性能。

12. 发明授权

US08350298B2 Hybrid material inversion mode GAA CMOSFET 有权
标题翻译：混合材料反演模式GAA CMOSFET
公开(公告)号：US08350298B2
公开(公告)日：2013-01-08
申请号：US12810619
申请日：2010-02-11
申请人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
发明人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
IPC分类号： H01L27/12 , H01L21/00 , H01L21/84 , H01L27/06 , H01L29/423 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84 , H01L27/0688 , H01L29/42392 , H01L29/78696
摘要： A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects.
摘要翻译： Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。第一通道和第二通道具有跑道形横截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。在反相模式下，器件具有混合材料，GAA结构，具有跑道形，高k栅介质层和金属栅极，从而实现高载流子迁移率，防止多晶硅栅极耗尽和短沟道效应。

13. 发明申请

US20110248354A1 HYBRID MATERIAL INVERSION MODE GAA CMOSFET 有权
标题翻译：混合材料反相模式GAA CMOSFET
公开(公告)号：US20110248354A1
公开(公告)日：2011-10-13
申请号：US12810619
申请日：2010-02-11
申请人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
发明人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
IPC分类号： H01L27/092
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84 , H01L27/0688 , H01L29/42392 , H01L29/78696
摘要： A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects.
摘要翻译： Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。第一通道和第二通道具有跑道形横截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。在反相模式下，器件具有混合材料，GAA结构，具有跑道形，高k栅介质层和金属栅极，从而实现高载流子迁移率，防止多晶硅栅极耗尽和短沟道效应。

14. 发明授权

US08877608B2 Method for preparing GOI chip structure 有权
标题翻译：制备GOI芯片结构的方法
公开(公告)号：US08877608B2
公开(公告)日：2014-11-04
申请号：US13825010
申请日：2012-09-25
申请人： Zengfeng Di , Lin Ye , Zhongying Xue , Miao Zhang
发明人： Zengfeng Di , Lin Ye , Zhongying Xue , Miao Zhang
IPC分类号： H01L21/46 , H01L21/762
CPC分类号： H01L21/76254
摘要： The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a SMART CUT technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.
摘要翻译：本发明提供了一种制备GOI芯片结构的方法，其中在该方法中，首先通过使用SMART CUT技术制造绝缘体上硅锗（SGOI）芯片结构，然后在SGOI上进行锗冷凝技术芯片结构，从而获得GOI芯片结构。由于采用智能切割技术制成的SGOI基本上在SGOI / BOX接口中没有错配位错，因此GOI的穿透位错密度最终降低。本发明的技术简单，可以实现高质量的GOI芯片结构，并且锗冷凝技术得到极大改善。离子注入技术和退火技术在目前的半导体工业中是相当成熟的技术，因此这种制备方法大大提高了半导体工业中锗浓缩技术的广泛应用的可能性。

15. 发明授权

US08580659B2 Method of fabricating high-mobility dual channel material based on SOI substrate 失效
标题翻译：基于SOI衬底制造高迁移率双通道材料的方法
公开(公告)号：US08580659B2
公开(公告)日：2013-11-12
申请号：US13262656
申请日：2011-07-25
申请人： Miao Zhang , Bo Zhang , Zhongying Xue , Xi Wang
发明人： Miao Zhang , Bo Zhang , Zhongying Xue , Xi Wang
IPC分类号： H01L21/20
CPC分类号： H01L21/76251 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation.
摘要翻译：本发明公开了一种制造基于SOI衬底的高迁移率双通道材料的方法，其中压缩应变SiGe在常规SOI衬底上外延生长以用作PMOSFET的沟道材料; Si在SiGe上表面生长，采用离子注入和退火等方法，使部分应变SiGe弛豫并向其上的Si层转移应变，形成作为NMOSFET的沟道材料的应变Si材料。通过简单的工艺和易于实现，该方法可以同时为NMOSFET和PMOSFET提供高迁移率沟道材料，可以很好地满足NMOSFET和PMOSFET器件同时提高性能的要求，从而为CMOS工艺提供潜在的沟道材料下一代。

16. 发明授权

US08330228B2 Hybrid material inversion mode GAA CMOSFET 失效
标题翻译：混合材料反演模式GAA CMOSFET
公开(公告)号：US08330228B2
公开(公告)日：2012-12-11
申请号：US12810694
申请日：2010-02-11
申请人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
发明人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L29/42392
摘要： A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.
摘要翻译： Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。第一通道和第二通道具有圆形截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。在反相模式下，电流流过整个圆柱形通道，以实现高载流子迁移率，降低低频噪声，防止多晶硅栅极耗尽和短沟道效应，并增加器件的阈值电压。

17. 发明申请

US20120129320A1 METHOD OF NISIGE EPITAXIAL GROWTH BY INTRODUCING AL INTERLAYER 失效
标题翻译：通过介绍AL InterLAYER的NISIGE外延生长方法
公开(公告)号：US20120129320A1
公开(公告)日：2012-05-24
申请号：US13260757
申请日：2011-07-25
申请人： Miao Zhang , Bo Zhang , Zhongying Xue , Xi Wang
发明人： Miao Zhang , Bo Zhang , Zhongying Xue , Xi Wang
IPC分类号： H01L21/20
CPC分类号： C30B29/52 , C30B1/00 , H01L21/28518 , H01L29/165 , H01L29/456
摘要： The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance.
摘要翻译：本发明公开了一种通过引入Al中间层的NiSiGe外延生长方法，包括在SiGe层的表面上沉积Al薄膜，随后在Al薄膜上沉积Ni层，然后在Ni之间进行退火处理 SiGe层的SiGe材料，形成NiSiGe材料。由于Al中间层的阻挡效应，NiSiGe层具有单晶结构，与SiGe衬底的平坦界面，厚度可达0.3nm，显着提高了界面性能。

18. 发明申请

US20110254101A1 HYBRID MATERIAL INVERSION MODE GAA CMOSFET 失效
标题翻译：混合材料反相模式GAA CMOSFET
公开(公告)号：US20110254101A1
公开(公告)日：2011-10-20
申请号：US12810694
申请日：2010-02-11
申请人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
发明人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L29/42392
摘要： A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.
摘要翻译： Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。第一通道和第二通道具有圆形截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。在反相模式下，电流流过整个圆柱形通道，以实现高载流子迁移率，降低低频噪声，防止多晶硅栅极耗尽和短沟道效应，并增加器件的阈值电压。

19. 发明申请

US20140199825A1 SILICON-GERMANIUM HETEROJUNCTION TUNNEL FIELD EFFECT TRANSISTOR AND PREPARATION METHOD THEREOF 有权
标题翻译：硅锗绝缘隧道场效应晶体管及其制备方法
公开(公告)号：US20140199825A1
公开(公告)日：2014-07-17
申请号：US13811268
申请日：2012-09-19
申请人： Jiantao Bian , Zhongying Xue , Zengfeng Di , Miao Zhang
发明人： Jiantao Bian , Zhongying Xue , Zengfeng Di , Miao Zhang
IPC分类号： H01L21/02 , H01L29/66
CPC分类号： H01L21/02532 , H01L21/02617 , H01L29/165 , H01L29/66356 , H01L29/66431 , H01L29/7391
摘要： A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects. The preparation method according to the present invention has a simple process, which is compatible with the CMOS process and is applicable to mass industrial production.
摘要翻译：提供硅/锗（SiGe）异质结隧道场效应晶体管（TFET）及其制备方法，其中器件的源极区域在硅锗（GeGe）或Ge区域上制造，漏极区域在Si区域中制造器件，从而在确保低OFF状态电流的同时获得高导通状态电流。本地Ge氧化和浓缩技术用于在某些地区实施高Ge含量的硅锗绝缘体（SGOI）或锗绝缘体（GOI）。在高Ge含量的SGOI或GOI中，Ge含量可控制在50％〜100％之间。另外，膜厚可以从5nm到20nm的范围内控制，便于实现器件工艺。在SiGe或Ge和Si的氧化和浓缩过程中，在SiGe或Ge和Si之间形成具有梯度Ge含量的SiGe异质结结构，从而消除缺陷。根据本发明的制备方法具有与CMOS工艺兼容的简单工艺，并且适用于大规模工业生产。

20. 发明申请

US20110254100A1 HYBRID MATERIAL ACCUMULATION MODE GAA CMOSFET 失效
标题翻译：混合材料累积模式GAA CMOSFET
公开(公告)号：US20110254100A1
公开(公告)日：2011-10-20
申请号：US12810648
申请日：2010-02-11
申请人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
发明人： Deyuan Xiao , Xi Wang , Miao Zhang , Jing Chen , Zhongying Xue
IPC分类号： H01L27/092
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L27/1211 , H01L29/42392 , H01L29/78696
摘要： A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented.
摘要翻译： Ge和Si混合材料堆积模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。第一通道和第二通道具有跑道形横截面并分别由p型Ge和n型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。在积累模式中，电流流过整个跑道状通道。所公开的器件具有高的载流子迁移率，高的器件驱动电流，并且保持器件的电气完整性。同时，防止了多晶硅栅极耗尽和短沟道效应。

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