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11. 发明申请

US20140072558A1 Activin Receptor Type II B Inhibitors Comprising DLK1 Extracellular Water-Soluble Domain 审中-公开
标题翻译：包含DLK1细胞外水溶性结构域的激活素受体II型B抑制剂
公开(公告)号：US20140072558A1
公开(公告)日：2014-03-13
申请号：US14009037
申请日：2012-04-03
申请人： Young Woo Park , Ki Won Jo , Donghee Lee , Eun Kyung Lee , Seil Jang , Chan Woong Park , Dong-Jin Kim , Hye Nan Kim , Yun Jung Park , Jae Eun Park , Ji Hyun Park , Seok Ho Yoo , Myeoung Hee Jang
发明人： Young Woo Park , Ki Won Jo , Donghee Lee , Eun Kyung Lee , Seil Jang , Chan Woong Park , Dong-Jin Kim , Hye Nan Kim , Yun Jung Park , Jae Eun Park , Ji Hyun Park , Seok Ho Yoo , Myeoung Hee Jang
IPC分类号： A61K39/395 , G01N33/68 , A61K38/17
CPC分类号： A61K39/3955 , A61K38/1709 , A61K38/177 , A61K39/39558 , C07K14/705 , C07K16/28 , C07K2317/21 , C07K2317/622 , C07K2317/75 , C07K2317/76 , C07K2317/92 , C07K2319/30 , G01N33/6893 , G01N33/74 , G01N2333/485 , A61K2300/00
摘要： The present invention relates to an activin receptor type II B (ACVR2B) inhibitor which comprises the delta-like 1 homolog (DLK1) extracellular water-soluble domain. More specifically, the present invention relates to an extracellular soluble domain of DLK1; fragments of the extracellular soluble domain of DLK1; mutants of the extracellular soluble domain of DLK1; a composition for suppressing ligand linkage with the ACVR2B receptor, which includes a fragment of the mutants as an active ingredient; and a pharmaceutical composition for prevention and treatment of diseases which comprises the same. The composition of the present invention competitively binds to the ACVR2B receptor and inhibits the binding of an ACVR2B ligand to the ACVR2B receptor, which inhibits protein signalling associated with such ligands, and will be useful for prevention and treatment of diseases associated therewith.
摘要翻译：本发明涉及包含δ-样1同系物（DLK1）细胞外水溶性结构域的激活素受体IIB型（ACVR2B）抑制剂。更具体地，本发明涉及DLK1的细胞外可溶性结构域; DLK1细胞外可溶性结构域的片段; DLK1细胞外可溶性结构域的突变体; 用于抑制与ACVR2B受体的配体键合的组合物，其包含突变体的片段作为活性成分; 以及用于预防和治疗包含该疾病的疾病的药物组合物。本发明的组合物竞争性地结合ACVR2B受体并且抑制ACVR2B配体与ACVR2B受体的结合，所述ACVR2B受体抑制与这种配体相关的蛋白质信号，并且将可用于预防和治疗与之相关的疾病。

12. 发明授权

US08546870B2 Semiconductor devices having gate structures with conductive patterns of different widths and methods of fabricating such devices 有权
标题翻译：具有具有不同宽度的导电图案的栅极结构的半导体器件和制造这种器件的方法
公开(公告)号：US08546870B2
公开(公告)日：2013-10-01
申请号：US12622594
申请日：2009-11-20
申请人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
发明人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L29/4234
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括依次层叠在半导体衬底上的第一电介质图案，数据存储图案和第二电介质图案。在第二电介质图案上提供第一导电图案。具有比第一导电图案更大的宽度的第二导电图案设置在第一导电图案上。

13. 发明申请

US20130115733A1 ETCHANT COMPOSITION AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR USING THE SAME 审中-公开
标题翻译：蚀刻组合物和使用该薄膜晶体管制造薄膜晶体管的方法
公开(公告)号：US20130115733A1
公开(公告)日：2013-05-09
申请号：US13547783
申请日：2012-07-12
申请人： Bong-Kyun KIM , Hong Sick PARK , Wang Woo LEE , Young Woo PARK , Shin Il CHOI , Sang-Woo KIM , Ki-Beom LEE , Dae-Woo LEE , Sam-Young CHO , Jeong-Heon CHOI
发明人： Bong-Kyun KIM , Hong Sick PARK , Wang Woo LEE , Young Woo PARK , Shin Il CHOI , Sang-Woo KIM , Ki-Beom LEE , Dae-Woo LEE , Sam-Young CHO , Jeong-Heon CHOI
IPC分类号： H01L21/465 , C09K13/06 , C09K13/00
CPC分类号： H01L21/32134 , C09K13/06 , C09K13/08 , C09K13/10 , H01L21/465 , H01L29/7869
摘要： Provided is an etchant composition. The etchant composition according to an exemplary embodiment of the present invention includes ammonium persulfate ((NH4)2)S2O8, an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, and water.
摘要翻译：提供了一种蚀刻剂组合物。根据本发明的示例性实施方案的蚀刻剂组合物包括过硫酸铵（（NH 4）2）S2O8，唑类化合物，水溶性胺化合物，含磺酸化合物，含硝酸盐化合物和水。

14. 发明申请

US20120326225A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20120326225A1
公开(公告)日：2012-12-27
申请号：US13529621
申请日：2012-06-21
申请人： SUNG-IL CHANG , Young-Woo Park
发明人： SUNG-IL CHANG , Young-Woo Park
IPC分类号： H01L29/792
CPC分类号： H01L21/764 , H01L21/76224 , H01L27/11563 , H01L27/11568 , H01L29/792
摘要： A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap.
摘要翻译：非易失性存储器件包括具有由具有沟槽和气隙的器件隔离区限定的有源区的衬底，位于沟槽下部的器件隔离图案，包括隧道绝缘层的存储单元层，顺序堆叠在有源区上并且其中一个从有源区向器件隔离区延伸的陷阱绝缘层和阻挡绝缘层包围气隙的顶部，其底部由不同于顶部和位于电池结构上的控制栅电极。绝缘层延伸的一个包括在对应于气隙的中心的区域处的凹部。

15. 发明授权

US08169018B2 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US08169018B2
公开(公告)日：2012-05-01
申请号：US12713736
申请日：2010-02-26
申请人： Jang-hyun You , Jin-taek Park , Young-woo Park , Jung-dal Choi
发明人： Jang-hyun You , Jin-taek Park , Young-woo Park , Jung-dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11565 , H01L27/11573 , H01L29/4234
摘要： A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The no-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer.
摘要翻译：非易失性存储器件包括包括单元区域和外围区域的半导体层，设置在半导体层的单元区域中的单元区域栅极结构，并且其中单元区域栅极结构包括隧道绝缘层和第一阻挡层绝缘层，第二阻挡绝缘层和第三阻挡绝缘层。非易失性存储器件还包括形成在半导体层的周边区域中的外围区域栅极结构。周边区域栅极结构包括：第一周边区域绝缘层，其包括与包含在隧道绝缘层中的材料相同的材料;以及第二周边区域绝缘层，其包括与包含在第三阻挡绝缘层中的材料相同的材料。

16. 发明申请

US20120086072A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF MANUFACTURE 审中-公开
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20120086072A1
公开(公告)日：2012-04-12
申请号：US13193702
申请日：2011-07-29
申请人： Jong-in Yun , Jin-Soo Lim , Han-soo Kim , Sung-Hwan Jang , Young-woo Park , Byoung-keun Son
发明人： Jong-in Yun , Jin-Soo Lim , Han-soo Kim , Sung-Hwan Jang , Young-woo Park , Byoung-keun Son
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/31111 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/40117 , H01L29/66833 , H01L29/7926
摘要： A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent.
摘要翻译：一种制造三维半导体存储器件的方法包括通过在衬底上交替地堆叠第一和第二材料层来形成薄层结构，形成穿透薄层结构的穿透凹陷，并使基底凹陷的顶部表面露出形成穿透薄层结构的垂直绝缘层以覆盖穿透凹陷的内壁，形成穿透穿孔凹陷处的垂直绝缘层的半导体图案，以插入到基板中，并且在薄的层间形成氧化物层通过氧化渗透凹陷的侧壁来形成层状结构和基底。

17. 发明申请

US20120056976A1 WIDE ANGLE LENS SYSTEM AND PHOTOGRAPHING APPARATUS 有权
标题翻译：宽角度透镜系统和摄影装置
公开(公告)号：US20120056976A1
公开(公告)日：2012-03-08
申请号：US13089518
申请日：2011-04-19
申请人： Yong-jae Lee , Young-woo Park
发明人： Yong-jae Lee , Young-woo Park
IPC分类号： H04N5/225 , G02B15/14
CPC分类号： G02B15/177 , G02B13/04
摘要： A wide angle lens system includes a first lens group having a negative refractive power and a second lens group having a positive refractive power arranged from an object side. The first lens group includes a first lens of a meniscus shape having a convex surface toward the object side, a second lens having a concave surface toward the object side, and a third lens having a convex surface toward the object side, and the second lens group includes a fourth lens having a convex surface toward the object side, a fifth lens having a concave surface toward the object side, and a sixth lens of a meniscus shape having a concave surface toward the object side. A photographing apparatus includes the wide angle lens system.
摘要翻译：广角透镜系统包括具有负折光力的第一透镜组和具有从物体侧布置的正折光力的第二透镜组。第一透镜组包括具有朝向物体侧的凸面的弯液面形状的第一透镜，具有朝向物体侧的凹面的第二透镜和朝向物体侧的凸面的第三透镜，第二透镜具有朝向物体侧的凸面的第四透镜，朝向物体侧的凹面的第五透镜和朝向物体侧的凹面的弯液面状的第六透镜。拍摄装置包括广角镜头系统。

18. 发明申请

US20110316165A1 Semiconductor Device and Method of Fabricating the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110316165A1
公开(公告)日：2011-12-29
申请号：US12912744
申请日：2010-10-27
申请人： JANG-HYUN YOU , JONG-MIN LEE , DONG-HWA KWAK , TAE-YONG KIM , JONG-HOON NA , YOUNG-WOO PARK , DONG-SIK LEE , JEE-HOON HAN
发明人： JANG-HYUN YOU , JONG-MIN LEE , DONG-HWA KWAK , TAE-YONG KIM , JONG-HOON NA , YOUNG-WOO PARK , DONG-SIK LEE , JEE-HOON HAN
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L21/0337 , H01L21/28273 , H01L21/3086 , H01L21/32139 , H01L21/76229 , H01L27/11521 , H01L27/11536 , H01L29/66825
摘要： A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines.
摘要翻译：半导体器件包括第一，第二和第三导线，每个导线具有形成在衬底上并且沿第一方向延伸的相应的线部分，并且具有相应的分支部分，该分支部分从相应线部分的端部沿与第一个方向中间导线的分支部分设置在外导电线的相应分支部分之间并且短于接触焊盘可以与导电线的这种分支部分一体形成。

19. 发明申请

US20110287612A1 Nonvolatile Memory Device, Method of Manufacturing the Nonvolatile Memory Device, and Memory Module and System Including the Nonvolatile Memory Device 有权
标题翻译：非易失性存储器件，制造非易失性存储器件的方法，以及包括非易失性存储器件的存储器模块和系统
公开(公告)号：US20110287612A1
公开(公告)日：2011-11-24
申请号：US13100488
申请日：2011-05-04
申请人： Jae-goo Lee , Young-woo Park , Byung-kwan You , Dong-sik Iee , Sang-yong Park
发明人： Jae-goo Lee , Young-woo Park , Byung-kwan You , Dong-sik Iee , Sang-yong Park
IPC分类号： H01L21/20
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L29/66477 , H01L29/7926
摘要： A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.
摘要翻译：非易失性存储器件包括衬底，从衬底突出的沟道层，围绕沟道层的栅极导电层，设置在沟道层和栅极导电层之间的栅极绝缘层以及与沟道间隔开的第一绝缘层并设置在栅极导电层的顶部和底部。栅极绝缘层在栅极导电层和第一绝缘层之间延伸。

20. 发明授权

US08045383B2 Non-volatile memory devices including dummy word lines and related structures and methods 有权
标题翻译：包括虚拟字线和相关结构和方法的非易失性存储器件
公开(公告)号：US08045383B2
公开(公告)日：2011-10-25
申请号：US11729169
申请日：2007-03-28
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Moreover, the first ground select line may be between the second ground select line and the first plurality of word lines, and the second ground select line may be between the first ground select line and the second plurality of word lines. Moreover, portions of the active region between the first and second ground select lines may be free of word lines, and a second spacing between the first and second ground select lines may be at least about 3 times greater than the first spacing. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。此外，第一接地选择线可以在第二接地选择线和第一多个字线之间，并且第二接地选择线可以在第一接地选择线和第二多个字线之间。此外，第一和第二接地选择线之间的有源区域的部分可以没有字线，并且第一和第二接地选择线之间的第二间隔可以比第一间隔大至少约3倍。还讨论了相关方法。

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