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11. 发明授权

US06184082B2 Method of fabricating dynamic random access memory 失效
标题翻译：制作动态随机存取存储器的方法
公开(公告)号：US06184082B2
公开(公告)日：2001-02-06
申请号：US09451136
申请日：1999-11-30
申请人： Yong-Fen Hsieh
发明人： Yong-Fen Hsieh
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/84 , H01L28/91
摘要： A method of fabricating a dynamic random access memory is described. The surrounding of a capacitor is covered with stop layers to prevent damage during the etching process for forming a bit line contact opening. A first dielectric layer is formed and it is patterned to form a capacitor opening therein. A conformal first stop layer is formed and covers the first dielectric layer and the capacitor opening. A part of the conformal first stop layer on the first source/drain is removed to form a self-aligned node contact opening. The capacitor is formed in the capacitor opening and the self-aligned node contact opening. A conformal second stop layer layer are formed over the substrate. A part of the second dielectric layer over the second source/drain, the conformal second stop layer, the first stop layer and the first dielectric layer underneath is removed to form a self-aligned bit line contact opening. A bit line is formed over the third dielectric layer and within the self-aligned bit line contact opening.
摘要翻译：描述了一种制造动态随机存取存储器的方法。电容器的周围被阻挡层覆盖，以防止在用于形成位线接触开口的蚀刻工艺期间的损坏。形成第一电介质层，并将其图案化以在其中形成电容器开口。形成共形的第一阻挡层并且覆盖第一电介质层和电容器开口。去除第一源极/漏极上的保形第一停止层的一部分以形成自对准节点接触开口。电容器形成在电容器开口和自对准节点接触开口中。在衬底上形成保形的第二阻挡层层。第二源极/漏极上的第二电介质层的一部分，共形第二阻挡层，第一阻挡层和下面的第一介电层被去除以形成自对准位线接触开口。在第三电介质层上并在自对准位线接触开口内形成位线。

12. 发明授权

US5989986A Method to inhibit the formation of ion implantation induced edge defects 失效
标题翻译：抑制离子注入诱导边缘缺陷形成的方法
公开(公告)号：US5989986A
公开(公告)日：1999-11-23
申请号：US857733
申请日：1997-05-16
申请人： Yong-Fen Hsieh
发明人： Yong-Fen Hsieh
IPC分类号： H01L21/265 , H01L21/285 , H01L21/8242
CPC分类号： H01L27/10844 , H01L21/26513 , H01L21/2652 , H01L21/28512
摘要： A method to determine a desired thickness for a surface layer through which ion implantation will take place in order to control the shape of the implantation profile to minimize the formation of flaws includes choosing a maximum angle .theta. between solid phase epitaxial regrowth fronts, determining a projected range of ion implantation distance Rp into the substrate and a projected standard deviation .DELTA.Rp along a first axis direction and a projected standard deviation .DELTA.Y along a second axis direction. These values are then substituted into the following equation to solve for thickness t of the surface layer: t=Rp+cos.theta.[[(.DELTA.Y sin .theta.).sup.2 +(.DELTA.Rp cos .theta.).sup.2 ].sup.0.5 ] After the layer is placed onto the substrate, the implantation step is carried out. Annealing is then performed to recrystallize the amorphous zone. The morphology of the surface being implanted through can also be modified in order to control the directions of recrystallization upon annealing.
摘要翻译：为了控制注入轮廓的形状以最小化缺陷的形成，确定用于表面层的表面层的期望厚度的方法包括选择固相外延再生长边之间的最大角度θ，确定投影沿着第一轴方向的离子注入距离Rp的范围和沿着第二轴方向的投影标准偏差DELTA Y的投影标准偏差DELTA Rp。然后将这些值代入以下等式来求解表面层的厚度t：t = Rp +cosθ[[（DELTA Ysinθ）2+（DELTA Rpcosθ）2] 0.5]在放置该层之后在基板上进行注入步骤。然后进行退火以使无定形区重结晶。为了控制退火时的再结晶方向，也可以对被植入的表面的形态进行修改。

13. 发明授权

US5956590A Process of forming a field effect transistor without spacer mask edge defects 失效
标题翻译：形成无间隔掩模边缘缺陷的场效应晶体管的工艺
公开(公告)号：US5956590A
公开(公告)日：1999-09-21
申请号：US907242
申请日：1997-08-06
申请人： Yong-Fen Hsieh , Shu-Jen Chen , Joe Ko
发明人： Yong-Fen Hsieh , Shu-Jen Chen , Joe Ko
IPC分类号： H01L21/265 , H01L21/266 , H01L21/336 , H01L29/08
CPC分类号： H01L29/66636 , H01L21/26586 , H01L21/266 , H01L29/0847 , H01L29/665
摘要： A field effect transistor which is not susceptible to mask edge detects at its gate spacer oxides. The transistor is formed upon a semiconductor substrate through successive layering of a gate oxide, a gate electrode and a gate cap oxide. A pair of curved gate spacer oxides are then formed covering opposite edges of the stack of the gate oxide, the gate electrode and the gate cap oxide. The semiconductor substrate is then etched to provide a smooth topographic transition from the gate spacer oxides to the etched semiconductor surface. Source/drain electrodes are then implanted into the etched semiconductor substrate and annealed to yield the finished transistor. A second embodiment of the field effect transistor possesses a polysilicon gate. Alter removal of the gate cap oxide, a metal layer may be deposited and sintered upon the polysilicon gate and the source/drain electrodes. The metal salicide layers formed upon the electrodes of the transistor have limited susceptibility to parasitic current leakage.
摘要翻译：对栅极边缘不敏感的场效应晶体管在其栅极间隔氧化物处检测。晶体管通过栅极氧化物，栅极电极和栅极氧化物的连续层叠形成在半导体衬底上。然后形成一对弯曲的栅间隔氧化物，其覆盖栅极氧化物，栅极电极和栅极氧化物的堆叠的相对边缘。然后蚀刻半导体衬底以提供从栅极间隔物氧化物到蚀刻的半导体表面的平滑的形貌转变。然后将源极/漏极注入到蚀刻的半导体衬底中并退火以产生成品晶体管。场效应晶体管的第二实施例具有多晶硅栅极。改变栅极氧化物的去除，金属层可以沉积并烧结在多晶硅栅极和源极/漏极上。形成在晶体管的电极上的金属硅化物层具有对寄生电流泄漏的敏感性的限制。

14. 发明授权

US5940678A Method of forming precisely cross-sectioned electron-transparent samples 失效
标题翻译：形成精确横截面电子透明样品的方法
公开(公告)号：US5940678A
公开(公告)日：1999-08-17
申请号：US927322
申请日：1997-09-11
申请人： Yih-Yuh Doong , Yong-Fen Hsieh
发明人： Yih-Yuh Doong , Yong-Fen Hsieh
IPC分类号： G01N1/32 , G01R31/307 , G01R31/26 , H01L21/66
CPC分类号： G01R31/307 , G01N1/32
摘要： A method of forming precisely cross-sectioned electron-transparent samples, includes removing, from a wafer, a chip containing a desired viewing site for analysis. At least one metallic mask is formed on a surface of the chip and over the viewing site using a focused ion beam microscope. Using a reactive ion etching technique, the chip is etched in a direction essentially perpendicular to the surface of the chip to form a thin viewing surface under the metallic mask. The thickness of the thin viewing surface is further reduced using a focused ion beam milling technique, to form an extremely thin electron-transparent sample.
摘要翻译：形成精确横截面的电子透明样品的方法包括从晶片去除含有所需观察位置的芯片用于分析。使用聚焦离子束显微镜在芯片的表面上和观察位置上形成至少一个金属掩模。使用反应离子蚀刻技术，在基本上垂直于芯片表面的方向上蚀刻芯片，以在金属掩模下形成薄的观察表面。使用聚焦离子束研磨技术进一步减小薄观察表面的厚度，以形成极薄的电子透明样品。

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