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11. 发明申请

US20130275934A1 SOLVING CONGESTION USING NET GROUPING 有权
标题翻译：使用网络分组的解决方案
公开(公告)号：US20130275934A1
公开(公告)日：2013-10-17
申请号：US13445128
申请日：2012-04-12
申请人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
发明人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method, system, and computer program product for solving a congestion problem in an integrated circuit (IC) design are provided in the illustrative embodiments. A congested g-edge is selected from a set of congested g-edges. A set of congesting nets is selected, wherein the set of congesting nets cause congestion in the selected congested g-edges by crossing the selected congested g-edge. A vacancy data structure corresponding to the selected congested g-edge is populated. A subset of the set of the congesting nets is selected. The subset of the set of the congesting nets is rerouted to a candidate g-edge identified in the vacancy data structure.
摘要翻译：在说明性实施例中提供了用于解决集成电路（IC）设计中的拥塞问题的方法，系统和计算机程序产品。从一组拥塞的g边缘中选择拥塞的g边。选择一组拥塞网络，其中所述拥塞网络集合通过穿过所选择的拥塞的g边缘而导致所选择的拥塞的g边缘中的拥塞。填充与所选择的拥塞的g边缘对应的空位数据结构。选择一组拥塞网络的子集。拥塞网络集合的子集被重新路由到在空白数据结构中标识的候选g边。

12. 发明授权

US08418113B1 Consideration of local routing and pin access during VLSI global routing 失效
标题翻译：在VLSI全局路由期间考虑本地路由和引脚接入
公开(公告)号：US08418113B1
公开(公告)日：2013-04-09
申请号：US13252067
申请日：2011-10-03
申请人： Charles J. Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
发明人： Charles J. Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.
摘要翻译：通过考虑本地路由和引脚访问来增强全局路由和拥塞评估。针对每个全局边缘基于相邻瓦片计算引脚信息，并且基于引脚信息减少边缘的布线轨迹容量。在全局路由之后，为了详细路由，线路轨道容量会增加先前的减少量。引脚信息可以包括相关瓦片的引脚数，引脚的Steiner树长度或引脚的相对位置。优选地通过在用于针的逻辑门的电路设计的特定金属层的轨道中产生阻塞来减少接线轨迹容量。阻塞轨道可以均匀地分布在给定边缘的接线轨道上。

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