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11. 发明授权

US06272577B1 Data processing system with master and slave devices and asymmetric signal swing bus 失效
标题翻译：数据处理系统具有主从设备和不对称信号摆幅总线
公开(公告)号：US06272577B1
公开(公告)日：2001-08-07
申请号：US08960951
申请日：1997-10-30
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G06F1300
CPC分类号： H04L25/028 , G06F13/40 , G06F13/4072 , G06F13/4077 , H04L25/026 , H04L25/0292 , Y02D10/14 , Y02D10/151
摘要： A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. A resynchronization circuit allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation so that each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. Redundant memory modules are included to replace defective memory modules, and replacement can be carried out through commands on the DASS bus. The memory device can be configured to simultaneously write a single input data stream to multiple memory modules or to perform high-speed interleaved read and write operations. In one embodiment, multiple memory devices are coupled to a common, high-speed I/O bus without requiring large bus drivers and complex bus receivers in the memory modules.
摘要翻译：一种存储器件，其利用通过单向非对称信号摆幅（DASS）总线并联到主I / O模块的多个存储器模块。这种结构提供了一个在电源电压的一半左右，高输入，高数据带宽，短访问时间，低延迟和高抗噪声的对称摆动的I / O方案。该器件利用改进的列存取电路，包括改进的地址排序电路和每个存储器模块内的数据放大器。同步电路允许器件使用相同的引脚进行同步和异步操作。每个存储器模块具有独立的地址和命令解码器，以实现独立操作，使得仅当在特定存储器模块内执行存储器访问操作时，每个存储器模块才被DASS总线上的命令激活。包括冗余内存模块以替换有缺陷的内存模块，并可通过DASS总线上的命令进行更换。存储器件可被配置为将单个输入数据流同时写入多个存储器模块或执行高速交错读写操作。在一个实施例中，多个存储器件耦合到公共的高速I / O总线，而不需要存储器模块中的大的总线驱动器和复杂的总线接收器。

12. 发明授权

US5898765A System and method for real-time exchange of customer data between telecommunications companies (quick pic) 失效
标题翻译：电信公司之间实时交换客户数据的系统和方法（快速图）
公开(公告)号：US5898765A
公开(公告)日：1999-04-27
申请号：US923872
申请日：1997-09-02
申请人： Eugene W. Teglovic , John B. Hedges , Douglas L. Wekamp , Theresa R. Jahelka , J. Wilbur Wayne Whitney, III , Winston Lee Davis, Jr. , Valerie J. Prothe
发明人： Eugene W. Teglovic , John B. Hedges , Douglas L. Wekamp , Theresa R. Jahelka , J. Wilbur Wayne Whitney, III , Winston Lee Davis, Jr. , Valerie J. Prothe
IPC分类号： H04Q3/00 , H04M15/00
CPC分类号： H04Q3/007 , H04Q2213/13103 , H04Q2213/13109 , H04Q2213/13196 , H04Q2213/13204 , H04Q2213/13349
摘要： A system and method for real-time exchange of customer information between telecommunications companies provides a significant reduction in the time required for completing a preferred inter-exchange carrier (PIC) order. It also provides significant reductions in the time required for other applications of customer information exchange, such as messages from a local exchange carrier (LEC) to an inter-exchange carrier (IEC) and customer inquiries. The present invention is an application of systems, and is referred to as Quick PIC. Quick PIC utilizes a telecommunications gateway that transmits a Customer Account Record Exchange (CARE) record, which format is defined by the ANSI T1.246 standard, using an OSI protocol stack that includes Common Management Information Protocol (CMIP) for the application layer. A CARE record can contain a PIC order, customer information inquiry, or customer information.
摘要翻译：用于电信公司之间实时交换客户信息的系统和方法大大减少了完成首选交换运营商（PIC）订单所需的时间。它还显着减少客户信息交换的其他应用所需的时间，例如来自本地交换运营商（LEC）到交换运营商（IEC）和客户查询的消息。本发明是系统的应用，并被称为快速PIC。快速PIC使用电信网关，该电信网关使用包括用于应用层的通用管理信息协议（CMIP）的OSI协议栈来传输客户帐户记录交换（CARE）记录，该格式由ANSI T1.246标准定义。 CARE记录可以包含PIC订单，客户信息查询或客户信息。

13. 发明授权

US5659550A Latent defect handling in EEPROM devices 失效
标题翻译： EEPROM器件中的潜在缺陷处理
公开(公告)号：US5659550A
公开(公告)日：1997-08-19
申请号：US494090
申请日：1995-06-23
申请人： Sanjay Mehrotra , Winston Lee , George Samachisa , Stephen J. Gross
发明人： Sanjay Mehrotra , Winston Lee , George Samachisa , Stephen J. Gross
IPC分类号： G01R31/28 , G06F11/10 , G06F12/16 , G11C16/06 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/50 , G06F11/00
CPC分类号： G11C29/76 , G11C29/02 , G11C29/025 , G11C29/50 , G11C29/82 , G11C29/832 , G11C29/88 , G06F11/1008 , G11C16/04 , G11C2029/5006
摘要： A memory system having a two dimensional array of EEPROM or Flash EEPROM cells is addressable by rows and columns. A word line is connected to the control gates of all the cells in each row, an erase line is connected to all the erase gates of each sector of cells, and a pair of bit lines are connected respectively to all the sources and drains of each column of cells. The memory system incorporates a word line current detector and an erase line current detector in addition to the usual bit line current detectors. The leakage current of each of the lines are measured after predetermined memory events such as program or erase operations. When a defective row or column is detected, it is electrically isolated from other columns by programming and is mapped out and replaced. Data recovery schemes include reading a defective column by a switched-memory-source-drain technique.
摘要翻译：具有EEPROM或闪存EEPROM单元的二维阵列的存储器系统可由行和列寻址。字线连接到每行的所有单元的控制栅极，擦除线连接到每个单元扇区的所有擦除栅极，并且一对位线分别连接到每个单元的所有源和漏极细胞柱。存储器系统除了通常的位线电流检测器之外还包括字线电流检测器和擦除线电流检测器。在预定的存储器事件例如编程或擦除操作之后测量每条线路的漏电流。当检测到有缺陷的行或列时，通过编程与其他列电隔离，并进行映射和更换。数据恢复方案包括通过开关式存储器 - 源极 - 漏极技术读取有缺陷的列。

14. 发明授权

US5172338A Multi-state EEprom read and write circuits and techniques 失效
标题翻译：多状态EEprom读写电路和技术
公开(公告)号：US5172338A
公开(公告)日：1992-12-15
申请号：US508273
申请日：1990-04-11
申请人： Sanjay Mehrotra , Eliyahou Harari , Winston Lee
发明人： Sanjay Mehrotra , Eliyahou Harari , Winston Lee
IPC分类号： G11C16/02 , G01R31/28 , G11C7/00 , G11C11/00 , G11C11/56 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/28 , G11C16/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/16 , G11C16/28 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C7/04 , G11C2211/5621 , G11C2211/5631 , G11C2211/5634 , G11C2211/5645
摘要： Improvements in the circuits and techniques for read, write and erase of EEprom memory enable non-volatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading is made relative to a set of threshold levels as provided by a corresponding set of reference cells which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells also exists for the whole memory chip acting as a master reference. In another embodiment, the reading is made relative to a set of threshold levels simultaneously by means of a one-to-many current mirror circuit. In improved write or erase circuits, verification of the written or erased data is done in parallel on a group of memory cells at a time and a circuit selectively inhibits further write or erase to those cells which have been correctly verified. Other improvements includes programming the ground state after erase, independent and variable power supply for the control gate of EEprom memory cells.
摘要翻译： EEprom存储器的读，写和擦除电路和技术的改进使非易失性多态存储器能够在更长的时间内以更高的性能运行。在用于正常读取和用于读取或擦除之间的读取和读取的改进电路进行验证之前，相对于由对应的一组参考单元提供的一组阈值电平进行读取，所述一组参考单元紧密地跟踪和调整由存储器呈现的变化细胞。在一个实施例中，存储器单元的每个闪存扇区具有其自己的用于读取扇区中的单元的参考单元，并且对于用作主参考的整个存储器芯片也存在一组参考单元。在另一个实施例中，通过一对多电流镜像电路同时进行相对于一组阈值电平的读取。在改进的写入或擦除电路中，写入或擦除的数据的验证一次在一组存储器单元上并行完成，并且电路选择性地禁止对已经被正确验证的那些单元进一步写入或擦除。其他改进包括对擦除后的基准状态进行编程，独立和可变的电源为EEprom存储器单元的控制栅极。

15. 发明授权

US08999786B1 Reducing source contact to gate spacing to decrease transistor pitch 有权
标题翻译：将源触点减小到栅极间距，以减小晶体管间距
公开(公告)号：US08999786B1
公开(公告)日：2015-04-07
申请号：US12052573
申请日：2008-03-20
申请人： Albert Wu , Pantas Sutardja , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
发明人： Albert Wu , Pantas Sutardja , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
IPC分类号： H01L21/336 , H01L29/788 , H01L21/027
CPC分类号： H01L29/41775 , H01L21/027 , H01L21/823425 , H01L27/11568 , H01L29/0847 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7835 , H01L29/792
摘要： Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in the active area; forming source and drain contacts over the source and drain regions, where a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor; and using one or more modified masks for forming doping profiles for the source region and the drain region.
摘要翻译：公开了具有减小的半导体器件中与栅极间隔的源极接触的晶体管的方法和结构。在一个实施例中，形成晶体管的方法可以包括：在晶体管的有源区上形成栅极; 形成与有源区域中的栅极对准的源区和漏区; 在源极和漏极区域上形成源极和漏极接触，其中晶体管的栅极至源极接触的间隔小于晶体管的栅极至漏极接触的间隔; 并且使用一个或多个修改的掩模来形成源极区和漏极区的掺杂分布。

16. 发明申请

US20110305095A1 System and Method for Memory Array Decoding 有权
标题翻译：用于存储器阵列解码的系统和方法
公开(公告)号：US20110305095A1
公开(公告)日：2011-12-15
申请号：US13214543
申请日：2011-08-22
申请人： Pantas Sutardja , Winston Lee
发明人： Pantas Sutardja , Winston Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/10 , G11C7/00 , G11C7/1006 , G11C7/18 , G11C8/12 , G11C8/14 , G11C2207/2209
摘要： A memory system including a memory array, and a read write/module. The memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, in which each memory cell is formed at a corresponding intersection of a bit line and a word line in the memory array. The read/write module is configured to control activation of at least two memory cells in the memory array during a read operation or a write operation, wherein the at least two memory cells activated by the read/write module are located on a different word line and a different bit line in the memory array, and wherein each memory cell coupled to a same bit line of the plurality of bit lines is configured to be written to or read from based on selection of the bit line.
摘要翻译：包括存储器阵列和读写/模块的存储器系统。存储器包括多个位线，多个字线和多个存储器单元，其中每个存储器单元形成在存储器阵列中位线和字线的相应交叉点处。读/写模块被配置为在读操作或写操作期间控制存储器阵列中的至少两个存储单元的激活，其中由读/写模块激活的至少两个存储单元位于不同的字线以及存储器阵列中的不同的位线，并且其中耦合到所述多个位线中的相同位线的每个存储器单元被配置为基于所述位线的选择被写入或从其读取。

17. 发明授权

US08004926B2 System and method for memory array decoding 有权
标题翻译：用于存储器阵列解码的系统和方法
公开(公告)号：US08004926B2
公开(公告)日：2011-08-23
申请号：US12364055
申请日：2009-02-02
申请人： Pantas Sutardja , Winston Lee
发明人： Pantas Sutardja , Winston Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/10 , G11C7/00 , G11C7/1006 , G11C7/18 , G11C8/12 , G11C8/14 , G11C2207/2209
摘要： A memory system includes Q memory blocks that each include M memory sub-blocks. The memory system also includes Q word line decoders that each are associated with a different one of the Q memory blocks. The memory system also includes a bit line decoder and Q×M switch modules. Each Q×M switch module selectively controls access to up to J of the M memory sub-blocks of the Q memory blocks. The Q word line decoders and the bit line decoder access less than M memory sub-blocks in at least two of the Q memory blocks during one of a read and write operation. M and Q are integers greater than 1, and J is an integer greater than or equal to 1.
摘要翻译：存储器系统包括每个包括M个存储器子块的Q个存储器块。存储器系统还包括Q个字线解码器，每个Q字线解码器与不同的Q存储器块相关联。存储器系统还包括位线解码器和Q×M开关模块。每个Q×M开关模块选择性地控制对Q个存储器块的M个存储器子块中的多达J个访问。在读取和写入操作期间，Q字线解码器和位线解码器在至少两个Q存储器块中访问少于M个存储器子块。 M和Q是大于1的整数，J是大于或等于1的整数。

18. 发明授权

US07888166B2 Method to form high efficiency GST cell using a double heater cut 有权
标题翻译：使用双加热器切割形成高效GST电池的方法
公开(公告)号：US07888166B2
公开(公告)日：2011-02-15
申请号：US12724266
申请日：2010-03-15
申请人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
IPC分类号： H01L21/00 , H01L29/18
CPC分类号： H01L27/2463 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described.
摘要翻译：本发明的实施例提供一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极。所述方法还包括在晶片的字线方向上执行平版印刷操作，以形成预热器元件布置，在跨过预热器元件布置的晶片的位线方向上执行平版印刷操作，以形成预加工元件 - 加热器元件，并且跨越预热器元件的一部分在字线方向上执行光刻操作，以形成邻近每个发射器的加热元件。还描述了其它实施例。

19. 发明授权

US07745809B1 Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench strips 有权
标题翻译：具有改进的发射体触点，改善的GST电池可靠性的超高密度相变存储器以及使用柱式微通道条带的高度匹配的UHD GST电池
公开(公告)号：US07745809B1
公开(公告)日：2010-06-29
申请号：US12062444
申请日：2008-04-03
申请人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
IPC分类号： H01L29/04
CPC分类号： H01L45/1233 , H01L27/0688 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Embodiments of the present invention provide an apparatus comprising a substrate comprising an emitter layer and at least one emitter interface adjacent to the emitter layer, and a metal protective layer on a top surface of the at least one emitter interface. A method of manufacturing such an apparatus is also disclosed. The method may include performing plasma nitridation directed at column micro-trench strips. Other embodiments are also described.
摘要翻译：本发明的实施例提供了一种装置，其包括：衬底，其包括发射极层和与发射极层相邻的至少一个发射极接口，以及在所述至少一个发射极接口的顶表面上的金属保护层。还公开了制造这种装置的方法。该方法可以包括执行针对柱状微沟槽条带的等离子体氮化。还描述了其它实施例。

20. 发明申请

US20080246015A1 METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT 有权
标题翻译：使用双重加热器切割形成高效GST细胞的方法
公开(公告)号：US20080246015A1
公开(公告)日：2008-10-09
申请号：US12060792
申请日：2008-04-01
申请人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
IPC分类号： H01L45/00
CPC分类号： H01L27/2463 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described.
摘要翻译：本发明的实施例提供一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极。所述方法还包括在晶片的字线方向上执行平版印刷操作，以形成预热器元件布置，在跨过预热器元件布置的晶片的位线方向上执行平版印刷操作，以形成预加工元件 - 加热器元件，并且跨越预热器元件的一部分在字线方向上执行光刻操作，以形成邻近每个发射器的加热元件。还描述了其它实施例。

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