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11. 发明授权

US4743969A Correlator 失效
标题翻译：相关者
公开(公告)号：US4743969A
公开(公告)日：1988-05-10
申请号：US832290
申请日：1986-02-21
申请人： Alwin F. G. Habeck , Walter H. Demmer , Jurgen Ruprecht , Detlef W. K. Oldach
发明人： Alwin F. G. Habeck , Walter H. Demmer , Jurgen Ruprecht , Detlef W. K. Oldach
IPC分类号： H04N5/08 , G06F17/15 , G06G7/19 , H03K5/00 , H04N5/10
CPC分类号： G06F17/15
摘要： An input signal comprising pulses in periodical intervals and being present as a series of digital sampling values is applied to a correlator for generating a correlator output signal which assumes an extreme value in the case of a pulse. The correlator comprises a chain of at least two cascaded delay members, the first of which receives the input signal. A pulse and pulse-free interval, respectively is associated with each delay member of the series, the delay members succeeding each other in the same manner as the pulses or pulse-free intervals occur. All but at most one delay member at the beginning or end of the chain can store just all sampling values of the associated pulse or pulse-free interval. The input signal of the first delay member and the output signals of all delay members are applied to a combination circuit which linearly combines and integrates the signals and forms the output signal of the correlator.
摘要翻译：包括周期性间隔的脉冲并作为一系列数字采样值存在的输入信号被施加到相关器，用于产生在脉冲的情况下呈现极值的相关器输出信号。相关器包括至少两个级联延迟构件的链，其中第一个接收输入信号。脉冲和无脉冲间隔分别与串联的每个延迟构件相关联，延迟构件以与脉冲或无脉冲间隔相同的方式彼此成功。在链的开始或结束处，除了最多一个延迟成员，只能存储相关脉冲或无脉冲间隔的所有采样值。第一延迟构件的输入信号和所有延迟构件的输出信号被施加到组合电路，该组合电路线性组合并积分信号并形成相关器的输出信号。

12. 发明授权

US4694326A Digital phase locked loop stabilization circuitry including a secondary digital phase locked loop which may be locked at an indeterminate frequency 失效
标题翻译：数字锁相环路稳定电路包括一个辅助数字锁相环，可以以不确定的频率锁定
公开(公告)号：US4694326A
公开(公告)日：1987-09-15
申请号：US845698
申请日：1986-03-28
申请人： Walter H. Demmer
发明人： Walter H. Demmer
IPC分类号： H04N9/45 , H03L7/06 , H03L7/087 , H03L7/099 , H04N9/87 , H04N11/04
CPC分类号： H04N9/8722 , H03L7/0994 , H04N11/04
摘要： A digital television receiver includes a first phase locked loop which develops a sampling clock signal that is locked to the horizontal line synchronizing signals components of a composite video signal. A second digital phase locked loop is clocked by the sampling clock signal and develops a digital signal that is phase locked to the color burst signal. This signal is used as a regenerated color subcarrier signal to synchronously demodulate the chrominance components of the composite video signal into I and Q color difference signals. To compensate for frequency instabilities in the regenerated subcarrier signal caused by frequency instabilities in the line-locked clock signal, a third digital phase locked loop develops an oscillatory signal which is phase locked to a reference signal generated by a crystal controlled oscillator. Control signals from the third phase locked loop are applied to circuitry which develops control signal that is independent of the crystal frequency. This control signal is applied to the second phase locked loop to substantially compensate for frequency instabilities related to the clock signal. Since the control signal applied to the second phase locked loop is independent of the frequency of the control, there is no need for manual adjustment of the crystal oscillator.
摘要翻译：数字电视接收机包括第一锁相环，其产生锁定到水平线的同步信号分量的采样时钟信号。第二数字锁相环由采样时钟信号计时，并产生与色同步信号锁相的数字信号。该信号用作再生彩色副载波信号，以将复合视频信号的色度分量同步解调为I和Q色差信号。为了补偿由线锁定时钟信号中的频率不稳定引起的再生子载波信号中的频率不稳定性，第三数字锁相环产生相位锁定到由晶体振荡器产生的参考信号的振荡信号。来自第三锁相环的控制信号被施加到产生独立于晶体频率的控制信号的电路。该控制信号被施加到第二锁相环，以基本上补偿与时钟信号相关的频率不稳定性。由于施加到第二锁相环的控制信号与控制的频率无关，所以不需要手动调整晶体振荡器。

13. 发明授权

US4672447A Circuit arrangement for synchronization of a signal 失效
标题翻译：用于信号同步的电路布置
公开(公告)号：US4672447A
公开(公告)日：1987-06-09
申请号：US770543
申请日：1985-08-29
申请人： Wilhelm Moring , Walter H. Demmer , Detlef W. K. Oldach
发明人： Wilhelm Moring , Walter H. Demmer , Detlef W. K. Oldach
IPC分类号： H04N5/04 , H03L7/06 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/18 , H03L7/191 , H04N5/12 , H03L7/00
CPC分类号： H04N5/126 , H03L7/087 , H03L7/191 , H03L7/091
摘要： In a circuit arrangement for synchronization of the phase of a frequency-divided signal with an edge of finite slope of an essentially periodic synchronizing signal with an oscillator supplying a clock signal, a frequency divider which generates the frequency-divided signal and a phase detector which comprises a first comparator for coarse phase detection, a second comparator for fine phase detection and a selector circuit which derives a resulting phase signal applied to the oscillator to control the frequency of the clock signal and originating from the first comparator in the case of large phase variations and from the second comparator in the case of small phase variations, precise adjustment to the edge is nevertheless achieved in the case of an amplitude-discrete synchronizing signal with limited time resolution because of the fact that the synchronizing signal is applied to the phase detector as a sequence of amplitude-discrete values which is formed by sampling the synchronizing signal with the clock signal, a sufficient number of amplitude stages being provided for the edge in the synchronizing signal.
摘要翻译：在用于使分频信号的相位与基本上周期性同步信号的边缘与提供时钟信号的振荡器同步的电路装置中，产生分频信号的分频器和相位检测器包括用于粗略相位检测的第一比较器，用于精细相位检测的第二比较器和选择器电路，其导出施加到振荡器的结果相位信号，以在大相位的情况下控制时钟信号的频率和源自第一比较器在小相位变化的情况下与第二比较器的差异，并且在具有有限的时间分辨率的幅度离散同步信号的情况下仍然实现对边缘的精确调整，因为同步信号被施加到相位检测器作为通过对同步物进行取样形成的振幅离散值序列 g信号与时钟信号，为同步信号中的边缘提供足够数量的幅度级。

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