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11. 发明授权

US07386739B2 Scheduling processor voltages and frequencies based on performance prediction and power constraints 失效
公开(公告)号：US07386739B2
公开(公告)日：2008-06-10
申请号：US11120899
申请日：2005-05-03
申请人： Soraya Ghiasi , Thomas Walter Keller, Jr. , Ramakrishna Kotla , Freeman Leigh Rawson, III
发明人： Soraya Ghiasi , Thomas Walter Keller, Jr. , Ramakrishna Kotla , Freeman Leigh Rawson, III
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , G06F11/3017 , G06F11/3058 , Y02D10/126 , Y02D10/172
摘要： A power management system schedules the voltage and frequency of processors in a data processing system based on two criteria. The first criterion is a prediction of the performance that the work currently running on the processor will experience at the different frequencies that are available. The second criterion is a system-wide constraint on the total power budget allocated to processors. Based on these criteria, low-level code sets the frequency and voltage of the processors in the system to match what the operating system is currently running on them.

12. 发明申请

US20140013126A1 BRANCH CIRCUIT DETERMINATION WITHOUT EXTERNAL SYNCHRONIZATION 有权
标题翻译：没有外部同步的分支电路确定
公开(公告)号：US20140013126A1
公开(公告)日：2014-01-09
申请号：US13542532
申请日：2012-07-05
申请人： Malcolm Scott Allen-Ware , Wael El-Essawy , Alexandre Peixoto Ferreira , Thomas Walter Keller, JR. , Karthick Rajamani , Juan Carlos Rubio
发明人： Malcolm Scott Allen-Ware , Wael El-Essawy , Alexandre Peixoto Ferreira , Thomas Walter Keller, JR. , Karthick Rajamani , Juan Carlos Rubio
IPC分类号： G06F1/26
CPC分类号： H02J13/002 , H04B3/54 , H04L12/6418
摘要： A method, system, and computer program product for relating a data processing system with a power branch circuit are provided in the illustrative embodiments. Each signal in a set of signals is combined with a power signal to form a set of combination signals, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. An amplitude of a corresponding signal in each combined signal in the set of combined signals is determined over a period. Using a discriminating logic, a determination is made whether the modulating signal is present in the power signal. Responsive to the discriminating logic producing an affirmative result, the data processing system is related with the power branch circuit.
摘要翻译：在说明性实施例中提供了用于将数据处理系统与功率分支电路相关联的方法，系统和计算机程序产品。一组信号中的每个信号与功率信号组合以形成一组组合信号，功率信号包括数据处理系统的第一功率使用和调制信号的第二功率使用。在一个周期中确定组合信号组中每个组合信号中对应信号的幅度。使用鉴别逻辑，确定调制信号是否存在于功率信号中。响应于产生肯定结果的识别逻辑，数据处理系统与功率分支电路相关。

13. 发明授权

US07444526B2 Performance conserving method for reducing power consumption in a server system 有权
标题翻译：降低服务器系统功耗的性能节省方法
公开(公告)号：US07444526B2
公开(公告)日：2008-10-28
申请号：US11154160
申请日：2005-06-16
申请人： Wesley Michael Felter , Thomas Walter Keller, Jr. , Karthick Rajamani , Cosmin Rusu
发明人： Wesley Michael Felter , Thomas Walter Keller, Jr. , Karthick Rajamani , Cosmin Rusu
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A method for managing power in a data processing system having multiple components includes determining a power budget for the system. Activity levels during a forthcoming time interval are then predicted for each of the components. Using the predicted activity levels, the power budget is allocated among the system components. An activity limit is then established for each component based on its corresponding portion of the power budget. The activity of a component is then monitored and, if the component's activity exceeds the component's corresponding activity limit, constrained. Determining the predicted level of activity may include determining a predicted number of instructions dispatched by a processor component or a predicted number of memory requests serviced for a system memory component. Allocating the power budget includes allocating each component its corresponding standby power and a share of the system power available for dynamic powering based on the expected levels of activity.
摘要翻译：一种用于在具有多个组件的数据处理系统中管理电力的方法包括确定系统的功率预算。然后对于每个组件预测在即将到来的时间间隔期间的活动水平。使用预测的活动级别，在系统组件之间分配功率预算。然后根据功率预算的相应部分为每个组件建立活动限制。然后监视组件的活动，如果组件的活动超过组件的相应活动限制，则会受到限制。确定预测的活动水平可以包括确定由处理器组件分派的指令的预测数量或为系统存储器组件服务的预测数量的存储器请求。分配功率预算包括基于预期的活动水平来分配每个组件其相应的待机功率和可用于动态供电的系统功率的份额。

14. 发明授权

US06772199B1 Method and system for enhanced cache efficiency utilizing selective replacement exemption 失效
标题翻译：使用选择性替代豁免来提高缓存效率的方法和系统
公开(公告)号：US06772199B1
公开(公告)日：2004-08-03
申请号：US09661661
申请日：2000-09-14
申请人： Thomas Walter Keller, Jr. , Karthikeyan P. Sankaralingam
发明人： Thomas Walter Keller, Jr. , Karthikeyan P. Sankaralingam
IPC分类号： G06F15167
CPC分类号： G06F17/30902 , G06F12/126 , H04L67/02
摘要： A method and system for enhanced cache efficiency is a cache associated with a server in a wide area network having multiple servers and clients. Objects retrieved from the network by a server are stored within a cache associated with the server and selected objects are designated as temporarily exempt from replacement based upon a preselected criterion, such as size or mandated quality of service for the client which requested the object. After the cache is full or nearly full, subsequently retrieved objects are stored by casting out one or more objects which are not exempt from replacement according to a specified replacement algorithm, such as Least Recently Utilized, or by casting out any object or objects, if all objects in the cache are designated as exempt from replacement.
摘要翻译：用于增强高速缓存效率的方法和系统是与具有多个服务器和客户端的广域网中的服务器相关联的高速缓存。由服务器从网络检索的对象被存储在与服务器相关联的高速缓存中，并且基于预先选择的标准（例如请求对象的客户端的规定或强制服务质量），将所选择的对象指定为暂时不被替换。在缓存已满或接近完成之后，通过根据指定的替换算法（例如“最近最少使用”）或通过抛出任何对象或对象来抛出一个或多个不被替换的对象来存储后续检索对象，如果缓存中的所有对象都被指定为免除替换。

15. 发明授权

US09009503B2 Branch circuit determination without external synchronization 有权
标题翻译：分支电路确定无需外部同步
公开(公告)号：US09009503B2
公开(公告)日：2015-04-14
申请号：US13542532
申请日：2012-07-05
申请人： Malcolm Scott Allen-Ware , Wael El-Essawy , Alexandre Peixoto Ferreira , Thomas Walter Keller, Jr. , Karthick Rajamani , Juan Carlos Rubio
发明人： Malcolm Scott Allen-Ware , Wael El-Essawy , Alexandre Peixoto Ferreira , Thomas Walter Keller, Jr. , Karthick Rajamani , Juan Carlos Rubio
IPC分类号： G06F1/26 , H02J13/00
CPC分类号： H02J13/002 , H04B3/54 , H04L12/6418
摘要： A method, system, and computer program product for relating a data processing system with a power branch circuit are provided in the illustrative embodiments. Each signal in a set of signals is combined with a power signal to form a set of combination signals, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. An amplitude of a corresponding signal in each combined signal in the set of combined signals is determined over a period. Using a discriminating logic, a determination is made whether the modulating signal is present in the power signal. Responsive to the discriminating logic producing an affirmative result, the data processing system is related with the power branch circuit.
摘要翻译：在说明性实施例中提供了用于将数据处理系统与功率分支电路相关联的方法，系统和计算机程序产品。一组信号中的每个信号与功率信号组合以形成一组组合信号，功率信号包括数据处理系统的第一功率使用和调制信号的第二功率使用。在一个周期中确定组合信号组中每个组合信号中对应信号的幅度。使用鉴别逻辑，确定调制信号是否存在于功率信号中。响应于产生肯定结果的识别逻辑，数据处理系统与功率分支电路相关。

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