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11. 发明授权

US08561037B2 Compiler for generating an executable comprising instructions for a plurality of different instruction sets 有权
标题翻译：用于生成包括用于多个不同指令集的指令的可执行程序的编译器
公开(公告)号：US08561037B2
公开(公告)日：2013-10-15
申请号：US11847169
申请日：2007-08-29
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： A software compiler is provided that is operable for generating an executable that comprises instructions for a plurality of different instruction sets as may be employed by different processors in a multi-processor system. The compiler may generate an executable that includes a first portion of instructions to be processed by a first instruction set (such as a first instruction set of a first processor in a multi-processor system) and a second portion of instructions to be processed by a second instruction set (such as a second instruction set of a second processor in a multi-processor system). Such executable may be generated for execution on a multi-processor system that comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set, and at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured.
摘要翻译：提供了一种软件编译器，其可操作用于生成包括多处理器系统中不同处理器可能采用的多个不同指令集的指令的可执行程序。编译器可以生成包括要由第一指令集（例如，多处理器系统中的第一处理器的第一指令集）处理的指令的第一部分和要由第一指令处理的指令的第二部分的可执行程序第二指令集（诸如多处理器系统中的第二处理器的第二指令集）。这样的可执行程序可以被生成用于在包括至少一个主机处理器的多处理器系统上执行，所述至少一个主处理器可以包括诸如公知的x86指令集之类的固定指令集，以及至少一个协处理器，其包括动态地可配置逻辑，使协处理器的指令集能够动态重新配置。

12. 发明授权

US08156307B2 Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set 有权
标题翻译：具有至少一个包括动态可重构指令集的处理器的多处理器系统
公开(公告)号：US08156307B2
公开(公告)日：2012-04-10
申请号：US11841406
申请日：2007-08-20
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F12/00 , G06F15/76
CPC分类号： G06F15/7867 , G06F9/24 , G06F9/3881 , G06F9/3897
摘要： A multi-processor system comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set. The system further comprises at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured. In this manner, the at least one host processor and the at least one dynamically reconfigurable co-processor are heterogeneous processors having different instruction sets. Further, cache coherency is maintained between the heterogeneous host and co-processors. And, a single executable file may contain instructions that are processed by the multi-processor system, wherein a portion of the instructions are processed by the host processor and a portion of the instructions are processed by the co-processor.
摘要翻译：多处理器系统包括至少一个主机处理器，其可以包括固定指令集，诸如公知的x86指令集。该系统还包括至少一个协处理器，其包括使协处理器的指令集能够动态重新配置的动态可重配置逻辑。以这种方式，至少一个主机处理器和至少一个动态可重配置协处理器是具有不同指令集的异构处理器。此外，在异构主机和协处理器之间保持高速缓存一致性。并且，单个可执行文件可以包含由多处理器系统处理的指令，其中指令的一部分由主机处理器处理，并且指令的一部分由协处理器处理。

13. 发明申请

US20090064095A1 COMPILER FOR GENERATING AN EXECUTABLE COMPRISING INSTRUCTIONS FOR A PLURALITY OF DIFFERENT INSTRUCTION SETS 有权
标题翻译：用于生成多个不同指令集的可执行包含指令的编译器
公开(公告)号：US20090064095A1
公开(公告)日：2009-03-05
申请号：US11847169
申请日：2007-08-29
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/447
摘要： A software compiler is provided that is operable for generating an executable that comprises instructions for a plurality of different instruction sets as may be employed by different processors in a multi-processor system. The compiler may generate an executable that includes a first portion of instructions to be processed by a first instruction set (such as a first instruction set of a first processor in a multi-processor system) and a second portion of instructions to be processed by a second instruction set (such as a second instruction set of a second processor in a multi-processor system). Such executable may be generated for execution on a multi-processor system that comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set, and at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured.
摘要翻译：提供了一种软件编译器，其可操作用于生成包括多处理器系统中不同处理器可能采用的多个不同指令集的指令的可执行程序。编译器可以生成包括要由第一指令集（例如，多处理器系统中的第一处理器的第一指令集）处理的指令的第一部分和要由第一指令处理的指令的第二部分的可执行程序第二指令集（诸如多处理器系统中的第二处理器的第二指令集）。这样的可执行程序可以被生成用于在包括至少一个主机处理器的多处理器系统上执行，所述至少一个主处理器可以包括诸如公知的x86指令集之类的固定指令集，以及至少一个协处理器，其包括动态地可配置逻辑，使协处理器的指令集能够动态重新配置。

14. 发明授权

US4514800A Digital computer system including apparatus for resolving names representing data items and capable of executing instructions belonging to general instruction sets 失效
标题翻译：数字计算机系统包括用于解析表示数据项的名称并能够执行属于一般指令集的指令的装置
公开(公告)号：US4514800A
公开(公告)日：1985-04-30
申请号：US266525
申请日：1981-05-22
申请人： Ronald H. Gruner , Gerald F. Clancy , Craig J. Mundie , Steven J. Wallach , Stephen I. Schleimer , Walter A. Wallach, Jr. , John K. Ahlstrom , David H. Bernstein , Michael S. Richmond , David A. Farber , John F. Pilat , Richard A. Belgard , Richard G. Bratt
发明人： Ronald H. Gruner , Gerald F. Clancy , Craig J. Mundie , Steven J. Wallach , Stephen I. Schleimer , Walter A. Wallach, Jr. , John K. Ahlstrom , David H. Bernstein , Michael S. Richmond , David A. Farber , John F. Pilat , Richard A. Belgard , Richard G. Bratt
IPC分类号： G06F9/35 , G06F9/40 , G06F13/00
CPC分类号： G06F9/4425 , G06F9/35
摘要： A digital computer system including a memory and a processor. The memory operates in response to memory commands received from the processor. Items of data stored in the memory include instructions to which the processor responds. Each instruction contains an operation code which belongs to one of several sets of operation codes. The meaning of a given operation code is determined by the operation code set to which the instruction belongs. Some of the instructions also contain names representing items of data used in the operation specified by the operation code. The processor includes an operation code decoding system which decodes the operation code as required for the instruction set to which it belongs, a name resolution system for deriving the address of the data item represented by a name from the name using an architectural base address contained in the name resolution system, and a control system which controls the operation of the processor. The processor performs a call operation and a return operation. Only the call operation and the return operation may change the current architectural base address. The memory further contains name table entries associated with the names. Each name table entry contains information used by the name resolution system when it resolves a name.
摘要翻译：一种包括存储器和处理器的数字计算机系统。存储器响应于从处理器接收的存储器命令而工作。存储在存储器中的数据项包括处理器响应的指令。每条指令都包含一个操作码，它属于几组操作码之一。给定操作代码的含义由指令所属的操作代码集确定。一些指令还包含表示由操作代码指定的操作中使用的数据项的名称。该处理器包括操作码解码系统，该系统根据其所属的指令集的需要对操作码进行解码，一个名称解析系统，用于从名称中导出由名称所代表的数据项的地址，名称解析系统和控制处理器的操作的控制系统。处理器执行呼叫操作和返回操作。只有通话操作和返回操作才能更改当前的架构基地址。内存还包含与名称相关联的名称表条目。每个名称表项包含名称解析系统在解析名称时使用的信息。

15. 发明授权

US09710384B2 Microprocessor architecture having alternative memory access paths 有权
公开(公告)号：US09710384B2
公开(公告)日：2017-07-18
申请号：US11969792
申请日：2008-01-04
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/0844 , G06F12/1027
CPC分类号： G06F12/0888 , G06F12/0844 , G06F12/0877 , G06F12/1027 , G06F2212/60 , G06F2212/68
摘要： The present invention is directed to a system and method which employ two memory access paths: 1) a cache-access path in which block data is fetched from main memory for loading to a cache, and 2) a direct-access path in which individually-addressed data is fetched from main memory. The system may comprise one or more processor cores that utilize the cache-access path for accessing data. The system may further comprise at least one heterogeneous functional unit that is operable to utilize the direct-access path for accessing data. In certain embodiments, the one or more processor cores, cache, and the at least one heterogeneous functional unit may be included on a common semiconductor die (e.g., as part of an integrated circuit). Embodiments of the present invention enable improved system performance by selectively employing the cache-access path for certain instructions while selectively employing the direct-access path for other instructions.

16. 发明申请

US20100115233A1 DYNAMICALLY-SELECTABLE VECTOR REGISTER PARTITIONING 审中-公开
标题翻译：动态可选选择矢量寄存器分区
公开(公告)号：US20100115233A1
公开(公告)日：2010-05-06
申请号：US12263232
申请日：2008-10-31
申请人： Tony Brewer , Steven J. Wallach
发明人： Tony Brewer , Steven J. Wallach
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/30189 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/3897 , G06F15/8084
摘要： The present invention is directed generally to dynamically-selectable vector register partitioning, and more specifically to a processor infrastructure (e.g., co-processor infrastructure in a multi-processor system) that supports dynamic setting of vector register partitioning to any of a plurality of different vector partitioning modes. Thus, rather than being restricted to a fixed vector register partitioning mode, embodiments of the present invention enable a processor to be dynamically set to any of a plurality of different vector partitioning modes. Thus, for instance, different vector register partitioning modes may be employed for different applications being executed by the processor, and/or different vector register partitioning modes may even be employed for use in processing different vector oriented operations within a given applications being executed by the processor, in accordance with certain embodiments of the present invention.
摘要翻译：本发明一般地涉及动态可选择的向量寄存器划分，更具体地涉及支持向量寄存器划分到多个不同的任何一个的动态设置的处理器基础设施（例如，多处理器系统中的协处理器基础设施）矢量分割模式。因此，本发明的实施例不是限于固定矢量寄存器分割模式，而是能够将处理器动态地设置为多个不同的矢量分割模式中的任何一个。因此，例如，可以对由处理器执行的不同应用采用不同的向量寄存器分割模式，和/或可以采用不同的向量寄存器分割模式来用于处理在由处理器，根据本发明的某些实施例。

17. 发明申请

US20090177843A1 MICROPROCESSOR ARCHITECTURE HAVING ALTERNATIVE MEMORY ACCESS PATHS 有权
标题翻译：具有替代存储器访问码的微处理器架构
公开(公告)号：US20090177843A1
公开(公告)日：2009-07-09
申请号：US11969792
申请日：2008-01-04
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0844 , G06F12/0877 , G06F12/1027 , G06F2212/60 , G06F2212/68
摘要： The present invention is directed to a system and method which employ two memory access paths: 1) a cache-access path in which block data is fetched from main memory for loading to a cache, and 2) a direct-access path in which individually-addressed data is fetched from main memory. The system may comprise one or more processor cores that utilize the cache-access path for accessing data. The system may further comprise at least one heterogeneous functional unit that is operable to utilize the direct-access path for accessing data. In certain embodiments, the one or more processor cores, cache, and the at least one heterogeneous functional unit may be included on a common semiconductor die (e.g., as part of an integrated circuit). Embodiments of the present invention enable improved system performance by selectively employing the cache-access path for certain instructions while selectively employing the direct-access path for other instructions.
摘要翻译：本发明涉及采用两个存储器访问路径的系统和方法：1）缓存访问路径，其中从主存储器取出块数据以加载到高速缓存，以及2）直接访问路径，其中单独地从主存储器中获取地址数据。系统可以包括利用高速缓存访问路径访问数据的一个或多个处理器核。系统还可以包括至少一个异构功能单元，其可操作以利用直接访问路径来访问数据。在某些实施例中，一个或多个处理器核心，高速缓存和至少一个异构功能单元可以包括在公共半导体管芯（例如，作为集成电路的一部分）上。本发明的实施例通过在选择性地使用用于其他指令的直接访问路径的情况下选择性地采用某些指令的高速缓存访问路径来实现改进的系统性能。

18. 发明申请

US20090055596A1 MULTI-PROCESSOR SYSTEM HAVING AT LEAST ONE PROCESSOR THAT COMPRISES A DYNAMICALLY RECONFIGURABLE INSTRUCTION SET 有权
标题翻译：具有至少一个包含动态可重构指令集的处理器的多处理器系统
公开(公告)号：US20090055596A1
公开(公告)日：2009-02-26
申请号：US11841406
申请日：2007-08-20
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F12/08 , G06F12/06 , G06F15/76
CPC分类号： G06F15/7867 , G06F9/24 , G06F9/3881 , G06F9/3897
摘要： A multi-processor system comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set. The system further comprises at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured. In this manner, the at least one host processor and the at least one dynamically reconfigurable co-processor are heterogeneous processors having different instruction sets. Further, cache coherency is maintained between the heterogeneous host and co-processors. And, a single executable file may contain instructions that are processed by the multi-processor system, wherein a portion of the instructions are processed by the host processor and a portion of the instructions are processed by the co-processor.
摘要翻译：多处理器系统包括至少一个主机处理器，其可以包括固定指令集，诸如公知的x86指令集。该系统还包括至少一个协处理器，其包括使协处理器的指令集能够动态重新配置的动态可重配置逻辑。以这种方式，至少一个主机处理器和至少一个动态可重配置协处理器是具有不同指令集的异构处理器。此外，在异构主机和协处理器之间保持高速缓存一致性。并且，单个可执行文件可以包含由多处理器系统处理的指令，其中指令的一部分由主机处理器处理，并且指令的一部分由协处理器处理。

19. 发明授权

US4926317A Hierarchical memory system with logical cache, physical cache, and address translation unit for generating a sequence of physical addresses 失效
标题翻译：具有逻辑高速缓存，物理缓存和地址转换单元的分层存储器系统，用于产生一系列物理地址
公开(公告)号：US4926317A
公开(公告)日：1990-05-15
申请号：US183355
申请日：1988-04-12
申请人： Steven J. Wallach , David M. Chastain , James R. Weatherford
发明人： Steven J. Wallach , David M. Chastain , James R. Weatherford
IPC分类号： G06F12/10 , G06F15/78
CPC分类号： G06F15/8069 , G06F12/1045
摘要： A vector processing computer (20) includes a memory control unit (22), main memory (99), a central processor (156), a service processing unit (42) and a plurality of input/output processors (54, 68). The central processor (156) includes a physical cache unit (100), an address translation unit (118), an instruction processing unit (126), an address scalar unit (142), a vector control unit (144), an odd pipe vector processing unit (148) and an even pipe vector processing unit (150). Vector elements are transmitted from memory, either main memory (99), a physical cache unit (100) or a logical cache (326) through a source bus (114) where the elements are alternately loaded into the vector processing units (148, 150). The resulting vectors are transmitted through a destination bus (114) to either the physical cache unit (100), the main memory (99), the logical cache (326) or to an input/output processor (54). In a still further aspect of the computer (20) there is included the logical data cache (326) which stores data at logical addresses such that the central processor (156) can store and retrieve data without the necessity of first making a translation from logical to physical address.
摘要翻译：矢量处理计算机（20）包括存储器控制单元（22），主存储器（99），中央处理器（156），服务处理单元（42）和多个输入/输出处理器（54,68）。中央处理器（156）包括物理缓存单元（100），地址转换单元（118），指令处理单元（126），地址标量单元（142），向量控制单元（144），奇数管矢量处理单元（148）和偶数管矢量处理单元（150）。矢量元素通过源总线（114）从存储器，主存储器（99），物理高速缓存单元（100）或逻辑高速缓存（326））传送，其中元件被交替加载到向量处理单元（148,150 ）。所得到的矢量通过目的地总线（114）发送到物理高速缓存单元（100），主存储器（99），逻辑高速缓存（326）或输入/输出处理器（54）。在计算机（20）的另一方面，包括逻辑数据高速缓存（326），其以逻辑地址存储数据，使得中央处理器（156）可以存储和检索数据，而不需要首先从逻辑到物理地址。

20. 发明授权

US4675810A Digital data processing system having a uniquely organized memory system using object-based addressing and in which operand data is identified by names accessed by name tables 失效
标题翻译：数字数据处理系统具有使用基于对象的寻址的唯一组织的存储器系统，并且其中操作数数据由名称表访问的名称标识
公开(公告)号：US4675810A
公开(公告)日：1987-06-23
申请号：US266536
申请日：1981-05-22
申请人： Ronald H. Gruner , Gerald F. Clancy , Craig J. Mundie , Stephen I. Schleimer , Steven J. Wallach , Richard G. Bratt , Edward S. Gavrin , Walter A. Wallach, Jr. , John K. Ahlstrom , Michael S. Richmond , David H. Bernstein , John F. Pilat , David A. Farber , Richard A. Belgard
发明人： Ronald H. Gruner , Gerald F. Clancy , Craig J. Mundie , Stephen I. Schleimer , Steven J. Wallach , Richard G. Bratt , Edward S. Gavrin , Walter A. Wallach, Jr. , John K. Ahlstrom , Michael S. Richmond , David H. Bernstein , John F. Pilat , David A. Farber , Richard A. Belgard
IPC分类号： G06F9/35 , G06F9/42 , G06F9/06
CPC分类号： G06F9/4426 , G06F9/35
摘要： A digital computer system having a memory system organized into procedure and data objects, each having a unique identifier code and an access control list, for storing items of information and a processor for processing data in response to instructions. The instructions contain operation codes and names representing data. Each name corresponds to a name table entry in a name table which contains information from which the processor determines the location and the format for the data. The name table entry specifies a base address of one of a set thereof which change value only when a call or a return instruction is executed. A name interpretation system fetches a name table entry, calculates the base address and a displacement using the name table entry and the current architectural base address and adds the base address to the displacement to form the address of the data represented by the name.
摘要翻译：一种数字计算机系统，其具有组织成过程和数据对象的存储器系统，每个存储器系统具有用于存储信息项的唯一标识符代码和访问控制列表，以及响应于指令处理数据的处理器。指令包含表示数据的操作代码和名称。每个名称对应于名称表中的名称表条目，其中包含处理器确定数据的位置和格式的信息。名称表条目指定仅当执行呼叫或返回指令时才改变值的其中一个的基地址。名称解释系统获取名称表项，使用名称表项和当前体系结构基地址计算基地址和位移，并将基地址添加到位移，以形成由名称表示的数据的地址。

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