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    • 11. 发明授权
    • Apparatus and method for correcting frequency offset in satellite digital video broadcasting system
    • 卫星数字视频广播系统频偏校正装置及方法
    • US07720182B2
    • 2010-05-18
    • US11636243
    • 2006-12-08
    • Tae-Hoon KimPan-Soo KimDae-Ig ChangDeock-Gil OhSeong-Jun Lee
    • Tae-Hoon KimPan-Soo KimDae-Ig ChangDeock-Gil OhSeong-Jun Lee
    • H04L1/00
    • H04B7/18523H04L27/2657H04L27/2672H04L27/2676
    • An apparatus and method for correcting a frequency offset in a satellite digital video broadcasting system includes a frequency response transformer for receiving a satellite digital video broadcasting signal and acquiring frequency responses divided into positive and negative frequency parts; a rotation/difference value calculation unit for selecting a frequency response inputted from the frequency response transformer and calculating a first value indicating a difference in area without rotation for the selected frequency response, and calculating a second value indicating a difference in area with rotation for the remaining frequency responses; a zero intersection point calculator for dividing an average slope of a straight line formed by the first and second values by the first value, and calculating a zero intersection point of an area difference value on the straight line; and a frequency offset estimator for correcting the zero intersection point to thereby estimate the frequency offset.
    • 一种用于校正卫星数字视频广播系统中的频率偏移的装置和方法包括:频率响应变换器,用于接收卫星数字视频广播信号并获取被分为正,负频率部分的频率响应; 旋转/差值计算单元,用于选择从频率响应变换器输入的频率响应,并计算指示所选择的频率响应的不旋转的面积差的第一值,并且计算表示针对所选择的频率响应的旋转区域的差异的第二值 剩余频率响应; 零交叉点计算器,用于将由第一和第二值形成的直线的平均斜率除以第一值,并计算直线上面积差值的零交叉点; 以及用于校正零交叉点从而估计频率偏移的频率偏移估计器。
    • 12. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20100109727A1
    • 2010-05-06
    • US12493712
    • 2009-06-29
    • Seong-Jun Lee
    • Seong-Jun Lee
    • H03L7/06
    • H03L7/0812
    • A semiconductor device for providing a reliable data valid window includes a drive control unit configured to output a driving power control signal in response to an internal clock and a command signal; a sub-drive voltage supply unit configured to supply sub-drive voltages; a main drive unit configured to generate a delay-locked loop (DLL) clock by driving the internal clock with a main drive voltage; a sub-drive unit configured to drive the internal clock with the sub-drive voltage in response to the driving power control signal; and a data output driver configured to drive and output a data signal in sync with the DLL clock, wherein the main drive unit and the sub-drive unit share their output terminal.
    • 用于提供可靠数据有效窗口的半导体器件包括:驱动控制单元,被配置为响应于内部时钟和命令信号输出驱动功率控制信号; 副驱动电压供给部,被配置为提供副驱动电压; 主驱动单元,被配置为通过以主驱动电压驱动内部时钟来产生延迟锁定环(DLL)时钟; 子驱动单元,被配置为响应于驱动功率控制信号而以副驱动电压驱动内部时钟; 以及数据输出驱动器,被配置为与DLL时钟同步地驱动和输出数据信号,其中主驱动单元和副驱动单元共享其输出端子。
    • 14. 发明申请
    • Semiconductor memory device capable of easily performing delay locking operation under high frequency system clock
    • 半导体存储器件能够在高频系统时钟下容易地执行延迟锁定操作
    • US20080136479A1
    • 2008-06-12
    • US11647645
    • 2006-12-29
    • Min-Young YouSeong-Jun Lee
    • Min-Young YouSeong-Jun Lee
    • H03L7/00
    • H03L7/0812G06F1/04G11C7/22G11C7/222H03K5/1565
    • A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.
    • 半导体存储器件包括:第一时钟缓冲器,用于响应于系统时钟信号的反相信号输出第一内部时钟信号,并用于响应于控制信号来校正第一内部时钟信号的占空比; 第二时钟缓冲器,用于响应于所述系统时钟信号输出第二内部时钟信号,并用于响应于所述控制信号来校正所述第二内部时钟信号的占空比; 模拟占空比校正电路,用于输出对应于第一和第二内部时钟信号的占空比的控制信号; 混合电路,用于混合第一和第二内部时钟信号,并输出其占空比被校正的第三内部时钟信号; 以及DLL电路,用于通过使用第三内部时钟信号输出延迟锁定时钟信号。
    • 15. 发明申请
    • Delay locked loop
    • 延迟锁定环路
    • US20080100353A1
    • 2008-05-01
    • US11819811
    • 2007-06-29
    • Seong-Jun LeeMin-Young You
    • Seong-Jun LeeMin-Young You
    • H03L7/06
    • H03L7/0814
    • A delay locked loop includes a buffer for outputting an internal clock by buffering an external clock, a delay block for delaying the internal clock in response to one of control signals or a selection signal, thereby outputting a delayed clock, a control signal generation block for generating at least one control signal according to a phase difference between the internal clock and a feedback clock generated by delaying the delayed clock by a delay time taken for the internal clock to be output, a selection block for outputting at least one selection signal in response to a signal instructing an off mode of the delay locked loop, thereby controlling a delay time in the delay block, and an output driver for driving the delayed clock.
    • 延迟锁定环包括缓冲器,用于通过缓冲外部时钟来输出内部时钟;延迟块,用于响应于控制信号之一或选择信号延迟内部时钟,从而输出延迟的时钟;控制信号产生块,用于 根据内部时钟与通过延迟延迟时钟产生的反馈时钟之间的相位差产生至少一个控制信号,所述延迟时间将被输出用于输出内部时钟的延迟时间;响应于输出至少一个选择信号的选择块 指示延迟锁定环的关闭模式的信号,从而控制延迟块中的延迟时间,以及用于驱动延迟时钟的输出驱动器。
    • 18. 发明授权
    • Liquid crystal display panel
    • 液晶显示面板
    • US08711303B2
    • 2014-04-29
    • US13178950
    • 2011-07-08
    • Yi LiSeong-Jun LeeYong-Kyu JangJae-Young LeeJu-Yeon Seo
    • Yi LiSeong-Jun LeeYong-Kyu JangJae-Young LeeJu-Yeon Seo
    • G02F1/1333
    • G02F1/133707G02F1/134336
    • A liquid crystal display panel that includes a number of pixel electrodes formed on a substrate and are located in a pixel region defined by gate lines and data lines that cross the gate lines. Each of the pixel electrodes located in the pixel region includes a number of sides, and at least one of the sides includes oblique lines and a protrusion formed by the oblique lines, and the pixel electrodes located in the pixel region and adjacent to each other in a first direction form a separation space that includes at least one protrusion, and a width of the separation space gradually reduces and gradually increases in a second direction crossing the first direction, and a singular point that controls the texture of liquid crystals is located at the narrowest width of the separation space.
    • 一种液晶显示面板,包括形成在基板上的多个像素电极,位于由栅极线和与栅极线交叉的数据线所限定的像素区域中。 位于像素区域中的每个像素电极包括多个侧面,并且至少一个侧面包括斜线和由斜线形成的突起,并且位于像素区域中并且彼此相邻的像素电极 第一方向形成包括至少一个突起的分离空间,并且分离空间的宽度在与第一方向交叉的第二方向上逐渐减小并逐渐增加,并且控制液晶结构的奇异点位于 最窄的分隔空间宽度。