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11. 发明授权

US5047660A High voltage high speed CCD clock driver 失效
标题翻译：高电压高速CCD时钟驱动器
公开(公告)号：US5047660A
公开(公告)日：1991-09-10
申请号：US432020
申请日：1989-11-06
申请人： Ram Kannegundla , Win-Chyi Chang
发明人： Ram Kannegundla , Win-Chyi Chang
IPC分类号： G11C19/28 , G11C27/04 , H04N5/335 , H04N5/378
CPC分类号： G11C19/285 , G11C27/04 , H04N5/335
摘要： A driver circuit, which is capable of operation in the 30 MHz frequency range and zero to +10 volts, is useful for driving charge coupled devices (CCDs). The driver circuit uses the parallel combination of an off the shelf bipolar integrated circuit capable of charging the CCD to about six volts and an off the shelf complementary field effect transistor transmission gate capable of charging the CCD to about +10 volts. The bipolar integrated circuit is capable of discharging the CCD from about +10 volts to zero volts (ground).
摘要翻译：能够在30MHz频率范围和零至+10V范围内工作的驱动电路对于驱动电荷耦合器件（CCD）是有用的。驱动器电路使用能够将CCD充电至约六伏特的现成的双极集成电路和能够将CCD充电至约+10伏的互补场效应晶体管传输门的并行组合。双极集成电路能够将CCD从大约+10伏特放电至零伏特（地）。

12. 发明授权

US5032740A Voltage level conversion of a clock signal 失效
标题翻译：时钟信号的电压电平转换
公开(公告)号：US5032740A
公开(公告)日：1991-07-16
申请号：US432021
申请日：1989-11-06
申请人： Ram Kannegundla
发明人： Ram Kannegundla
IPC分类号： H03K5/04 , H03K5/15 , H03K19/0185
CPC分类号： H03K5/04 , H03K19/018557 , H03K5/1504
摘要： The number of wires needed to supply a CCD sensor with the necessary control pulses is reduced by deriving such control pulses as the reset, sample and clamp pulses at the CCD sensor from an available source such as the horizontal clock signal. Although the horizontal clock signal may be significantly different in d-c reference level and amplitude from the needed control pulses, the control pulses are generated by translating the horizontal clock signal to a signal of the needed d-c reference level and amplitude and properly timing the generation of the necessary control pulses.
摘要翻译：通过从诸如水平时钟信号的可用源导出CCD传感器上的复位，采样和钳位脉冲等控制脉冲，可减少为CCD传感器提供所需控制脉冲所需的电线数量。虽然水平时钟信号在直流参考电平和幅度与所需的控制脉冲之间可能会有显着差异，但是通过将水平时钟信号转换为所需的直流参考电平和振幅的信号并适当地定时生成必要的控制脉冲。

13. 发明授权

US5530475A Image sensor with oversized vertical shift registers for marker pixel generation 失效
标题翻译：具有超大垂直移位寄存器的图像传感器，用于标记像素生成
公开(公告)号：US5530475A
公开(公告)日：1996-06-25
申请号：US346723
申请日：1994-11-30
申请人： Ram Kannegundla , Charles V. Stancampiano
发明人： Ram Kannegundla , Charles V. Stancampiano
IPC分类号： H04N5/3728 , H04N5/376 , H04N5/335
CPC分类号： H04N3/1575 , H04N3/155
摘要： A method and apparatus for generating timing signals within the sensor in an imaging system by making provisions internally within a sensor that allows the sensor to generate the timing signals which are then output to the system to control the image sensor timing This alleviates the system from the responsibility of counting pixels and lines. The sensor will give at predetermined times, outputs which have the same wave form as the normal video output but with a much higher amplitude than the maximum video output recognized by the image processing system. These output signals will identify the end of the line and likewise will identify the end of the frame (or field). The resulting sensor can maintain its own timing sequence accurately tracking the time for lines and frame readout.
摘要翻译：一种用于在成像系统内在传感器内产生定时信号的方法和装置，其通过在传感器内部进行设置，允许传感器产生定时信号，然后输出到系统以控制图像传感器定时。这样可以使系统从计数像素和线的责任。传感器将在预定时间给出具有与正常视频输出相同波形的输出，但是具有比由图像处理系统识别的最大视频输出高得多的幅度。这些输出信号将标识行的末尾，同样将标识帧（或字段）的结尾。所得到的传感器可以保持其自己的定时序列，准确地跟踪线和帧读出的时间。

14. 发明授权

US5440342A Logic system and method for controlling any one of different charge coupled device image sensors to provide video image signals in accordance with a television standard 失效
标题翻译：用于控制不同电荷耦合器件图像传感器中的任一个的逻辑系统和方法，以根据电视标准提供视频图像信号
公开(公告)号：US5440342A
公开(公告)日：1995-08-08
申请号：US5323
申请日：1993-01-15
申请人： Ram Kannegundla
发明人： Ram Kannegundla
IPC分类号： H04N5/225 , H04N5/335 , H04N5/341 , H04N5/372 , H04N7/01
CPC分类号： H04N5/335
摘要： Apparatus and method for controlling a charge coupled device (CCD) image sensor provides in accordance with a television standard horizontal and vertical CCD control signals. The apparatus includes a frequency generator, a standard timing generator, a pixel clock generator, and a small number of additional timers and logic units which are driven by signals from the generators to generate the vertical and horizontal CCD control signals. The frequency of operation of the pixel clock generator is selectable in accordance with a number of pixels per horizontal line of the CCD image sensor. Various CCD image sensors having different numbers of pixels per horizontal line may be used. The method includes generating a plurality of precisely timed pulses referenced to television standard synchronizing and control signals, and logically combining these pulses and standard signals to generate the vertical and horizontal CCD control signals.
摘要翻译：用于控制电荷耦合器件（CCD）图像传感器的装置和方法根据电视标准提供水平和垂直CCD控制信号。该装置包括频率发生器，标准定时发生器，像素时钟发生器以及由来自发生器的信号驱动以生成垂直和水平CCD控制信号的附加定时器和逻辑单元。像素时钟发生器的操作频率可以根据CCD图像传感器的每条水平线的像素数量来选择。可以使用每个水平线具有不同像素数的各种CCD图像传感器。该方法包括产生参考电视标准同步和控制信号的多个精确定时脉冲，以及逻辑地组合这些脉冲和标准信号以产生垂直和水平CCD控制信号。

15. 发明授权

US5321509A Apparatus and method for controlling a charge coupled device image sensor to provide sequential output of video image signals 失效
标题翻译：用于控制电荷耦合器件图像传感器以提供视频图像信号的顺序输出的装置和方法
公开(公告)号：US5321509A
公开(公告)日：1994-06-14
申请号：US5326
申请日：1993-01-15
申请人： Ram Kannegundla
发明人： Ram Kannegundla
IPC分类号： H04N5/06 , H04N5/335 , H04N5/343 , H04N5/372 , H04N5/067
CPC分类号： H04N5/335 , H04N5/06
摘要： Apparatus and method for controlling a charge coupled device (CCD) image sensor provides, in accordance with a television standard, horizontal and vertical CCD control signals to obtain a purely sequential mode of operation on the one hand, and alternatively a modified mode of operation to permit image signals to be viewed directly on a standard viewfinder display. The apparatus includes a frequency generator, a standard timing generator, a pixel clock generator, and a small number of additional timers and logic units which are driven by signals from the generators to selectably generate the vertical and horizontal CCD control signals for the alternate modes of operation. The method includes generating a plurality of precisely timed pulses referenced to television standard synchronizing and control signals, and logically combining these pulses and standard signals to generate the vertical and horizontal CCD control signals.
摘要翻译：用于控制电荷耦合器件（CCD）图像传感器的装置和方法根据电视标准提供水平和垂直CCD控制信号，以获得纯粹的顺序操作模式，另一方面，修改的操作模式允许在标准取景器显示器上直接观看图像信号。该装置包括频率发生器，标准定时发生器，像素时钟发生器，以及少量额外的定时器和逻辑单元，其由来自发生器的信号驱动，以可选择地产生垂直和水平CCD控制信号，用于替代模式操作。该方法包括产生参考电视标准同步和控制信号的多个精确定时脉冲，以及逻辑地组合这些脉冲和标准信号以产生垂直和水平CCD控制信号。

16. 发明授权

US5321315A Tracking control pulse generation for variable frame rate CCD sensors for electronic imaging applications 失效
标题翻译：用于电子成像应用的可变帧率CCD传感器的跟踪控制脉冲生成
公开(公告)号：US5321315A
公开(公告)日：1994-06-14
申请号：US848620
申请日：1992-03-09
申请人： Ram Kannegundla
发明人： Ram Kannegundla
IPC分类号： H03K5/135 , H04N5/341 , H04N5/357 , H04N5/372 , H04N5/376 , H03K3/017
CPC分类号： H04N5/3765 , H03K5/135 , H04N5/357 , H04N5/372
摘要： Reset, clamp, and sample pulses for a CCD sensor for electronic imaging applications are generated which have their leading edges delayed with respect to the leading edges of corresponding pixel clock pulses by substantially constant proportions of the pixel clock period independently of pixel frequency. To do this, a first auxiliary 50 percent duty cycle pulse train is generated having a frequency 4 times the pixel frequency. A divide by 4 counter receives the first auxiliary train and produces both the pixel clock itself and a second auxiliary 50 percent duty cycle pulse train having a frequency twice the pixel frequency. A 3 to 8 line decoder receives the pixel clock and both auxiliary trains to produce eight separate trains of pulses having the pixel frequency and a substantially 12.5 percent duty cycle. Each of the eight separate trains has the leading edge of its pulses delayed by substantially an eighth of the pixel clock period from the leading edge of the pulses of a different one of the eight separate trains. Different ones of the eight separate rains are selected to form the desired trains of reset, clamp, and sample pulses.
摘要翻译：产生用于电子成像应用的CCD传感器的复位，钳位和采样脉冲，其具有相对于相应像素时钟脉冲的前沿沿着像素频率的基本上恒定的像素时钟周期的比例而延迟其前沿。为此，产生具有4倍于像素频率的频率的第一辅助50％占空比脉冲串。 4位计数器的除法器接收第一辅助列，并产生像素时钟本身和具有频率为像素频率两倍的第二辅助50％占空比脉冲串。 3至8行解码器接收像素时钟和两个辅助列，以产生具有像素频率和基本上12.5％占空比的八个单独的脉冲序列。八个单独列车中的每一个具有其脉冲的前沿从八个分开的列中不同的一个的脉冲的前沿延迟了像素时钟周期的大致八分之一。选择八个独立雨水中的不同的降雨以形成所需的重置，夹紧和采样脉冲列。

17. 发明授权

US5319263A Power saving impedance transformation circuit for CCD image sensors 失效
标题翻译： CCD图像传感器的省电阻抗变换电路
公开(公告)号：US5319263A
公开(公告)日：1994-06-07
申请号：US890402
申请日：1992-05-29
申请人： Ram Kannegundla , Teh-Hsuang Lee
发明人： Ram Kannegundla , Teh-Hsuang Lee
IPC分类号： H03F1/56 , H03F3/50 , H03K19/018 , G11C27/02
CPC分类号： H03F1/56 , H03F3/50
摘要： A power saving impedance transformation circuit for receiving a d-c biased signal comprises a junction transistor connected to operate as an emitter follower, means for connecting the base of the transistor to receive the signal, an operational amplifier having both inverting and non-inverting inputs, a first resistor connected between the emitter of the transistor and the operational amplifier inverting input, a second resistor equal to the first resistor in resistance and having one end connected to the operational amplifier inverting input, resistive means for connecting the other end of the second resistor to a first voltage source of a polarity which, in cooperation with the signal, forward biases the emitter-base junction of the transistor, the emitter-base junction of the transistor receiving its forward bias from the first voltage source exclusively through the first and second resistors and the resistive means, and means for connecting the collector of the transistor to a second voltage source of a polarity opposite to that of the first voltage source.
摘要翻译：用于接收直流偏置信号的功率节省阻抗变换电路包括连接用作射极跟随器的结型晶体管，用于连接晶体管的基极以接收信号的装置，具有反相和非反相输入的运算放大器，连接在晶体管的发射极和运算放大器反相输入端之间的第一电阻器，等于第一电阻器的第二电阻器，其一端连接到运算放大器反相输入端，用于将第二电阻器的另一端连接到一个极性的第一电压源，与该信号协同工作，正向偏置晶体管的发射极 - 基极结，晶体管的发射极 - 基极结从第一电压源接收其正向偏置，仅通过第一和第二电阻和电阻装置，以及用于将晶体管的集电极连接到断路器的装置 nd电压源的极性与第一电压源的极性相反。

18. 发明授权

US5294848A Wide variation timed delayed digital signal producing circuit 失效
标题翻译：宽变化定时延迟数字信号产生电路
公开(公告)号：US5294848A
公开(公告)日：1994-03-15
申请号：US966646
申请日：1992-10-26
申请人： Ram Kannegundla
发明人： Ram Kannegundla
IPC分类号： H03K5/00 , H03K5/13 , H03K17/28
CPC分类号： H03K5/13 , H03K2005/00163 , H03K2005/00234
摘要： A time delayed digital circuit includes three circuits, each of which includes two inverters used in charging and discharging a capacitor to produce a precisely delayed output digital signal which can have wide variations.
摘要翻译：时间延迟数字电路包括三个电路，每个电路包括用于对电容器进行充电和放电的两个反相器，以产生可以具有宽变化的精确延迟的输出数字信号。

19. 发明授权

US5285286A Apparatus for testing image sensors that simultaneously output multiple image blocks 失效
标题翻译：用于测试同时输出多个图像块的图像传感器的装置
公开(公告)号：US5285286A
公开(公告)日：1994-02-08
申请号：US825224
申请日：1992-01-24
申请人： Ram Kannegundla
发明人： Ram Kannegundla
IPC分类号： H04N5/335 , H04N5/372 , H04N17/00
CPC分类号： H04N5/335 , H04N17/002
摘要： An apparatus for producing a visual image stored in a multi-output CCD image sensor for CCD image analysis which has a plurality of analog shift registers. Analog multiplexers are used to eliminate the need for a frame store.
摘要翻译：一种存储在具有多个模拟移位寄存器的用于CCD图像分析的多输出CCD图像传感器中的视觉图像的装置。模拟多路复用器用于消除对帧存储的需要。

20. 发明授权

US5264945A Contact array scanners with circulating memory 失效
标题翻译：与循环记忆接触阵列扫描仪
公开(公告)号：US5264945A
公开(公告)日：1993-11-23
申请号：US777860
申请日：1991-10-16
申请人： Ram Kannegundla , Bruce C. Burkey
发明人： Ram Kannegundla , Bruce C. Burkey
IPC分类号： H04N1/193 , H04N5/335 , H04N5/372 , H04N3/14
CPC分类号： H04N1/193 , H04N3/1593 , H04N5/335
摘要： A plurality of linear image sensors of a contact array scanner are read out at relatively low sensor pixel rates using only a limited number of expensive digital components. For a contact array scanner having sensors with both forward and reverse readouts, outputs are selected and read together in parallel from successive pairs of forward sensor readouts. Individual outputs from each of the forward readout pairs are sequentially sampled and held and the samples from each of the forward readout pairs are digitized. Outputs are also selected and read together in parallel from successive pairs of reverse sensor readouts. Individual outputs from each of the reverse readout pairs are sequentially sampled and held and the samples from each of the reverse readout pairs are digitized. Digitized samples from successive ones of the forward readout pairs are written into alternate ones of two pairs of first in first out digital memories and digitized samples from the reverse readout pairs are written into alternate ones of two pairs of last in first out memories. Finally, the contents of each pair of first in first out memories and the contents of each pair of last in first out memories are read out while the next pairs of digitized samples are being written into the other sets of first in first out and last in first out digital memories.
摘要翻译：接触阵列扫描器的多个线性图像传感器仅使用有限数量的昂贵的数字部件以相对低的传感器像素速率读出。对于具有正向和反向读出的传感器的接触阵列扫描器，从连续的正向传感器读出对中选择并并行地读出输出。来自每个正向读出对的各个输出被依次采样和保持，并且来自每个正向读出对的采样被数字化。输出也从连续的反向传感器读数对中并行选择和读出。来自每个反向读出对的单个输出被顺序采样和保持，并且来自每个反向读出对的样本被数字化。来自连续的正向读出对的数字化采样被写入两对先进先出的数字存储器中的交替的样本，并且来自反向读出对的数字化样本被写入两对最后一个先出存储器中的替代的样本。最后，读出每一对先进先出存储器的内容和每对最后一个先出存储器的内容，同时将下一对数字化样本写入其他先进先出的最后一组先出数字记忆。

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