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11. 发明授权

US5694363A Reading circuit for memory cell devices having a low supply voltage 失效
标题翻译：具有低电源电压的存储单元器件的读取电路
公开(公告)号：US5694363A
公开(公告)日：1997-12-02
申请号：US638976
申请日：1996-04-25
申请人： Cristiano Calligaro , Roberto Gastaldi , Nicola Telecco , Guido Torelli
发明人： Cristiano Calligaro , Roberto Gastaldi , Nicola Telecco , Guido Torelli
IPC分类号： G11C11/419 , G11C7/06 , G11C7/00 , G11C7/02
CPC分类号： G11C7/065
摘要： A device for reading memory cells, wherein the device contains two branches, wherein each branch comprises, connected in cascade, an electronic switch, an active element reactively connected to the active element of the other branch, so as to form a voltage amplifier. Each active element is controlled by means of a high impedance circuit element. A microswitch connects the two branches together is inserted between the two active elements.
摘要翻译：一种用于读取存储器单元的装置，其中该装置包含两个分支，其中每个分支包括级联连接的电子开关，与另一分支的有源元件反应地连接的有源元件，以形成电压放大器。每个有源元件通过高阻抗电路元件来控制。将两个分支连接在一起的微动开关插入两个活动元件之间。

12. 发明授权

US07580291B2 Data register with efficient erase, program verify, and direct bit-line memory access features 有权
标题翻译：数据寄存器具有高效擦除，程序验证和直接位线存储器访问功能
公开(公告)号：US07580291B2
公开(公告)日：2009-08-25
申请号：US11422960
申请日：2006-06-08
申请人： Nicola Telecco
发明人： Nicola Telecco
IPC分类号： G11C16/06 , G11C7/10 , G11C7/02
CPC分类号： G06F13/28 , G11C16/3436
摘要： A programmable memory device circuit comprising a sense and programming circuit, a latch circuit, a verify circuit for coupling the latch circuit logic value to a shared indicator line, and a direct memory access circuit coupled to the verify circuit. The DMA circuit couples a bit line to the verify circuit, and the verify circuit couples the direct memory access circuit to a shared verify indicator and DMA line.
摘要翻译：一种可编程存储器件电路，包括感测和编程电路，锁存电路，用于将锁存电路逻辑值耦合到共享指示线的验证电路，以及耦合到验证电路的直接存储器存取电路。 DMA电路将位线耦合到验证电路，并且验证电路将直接存储器访问电路耦合到共享验证指示符和DMA线。

13. 发明申请

US20090040825A1 NOVEL ROW REDUNDANCY SCHEME IN A MULTICHIP INTEGRATED MEMORY 有权
标题翻译：在多媒体集成存储器中的新方法冗余方案
公开(公告)号：US20090040825A1
公开(公告)日：2009-02-12
申请号：US11835572
申请日：2007-08-08
申请人： Vijay P. Adusumilli , Nicola Telecco
发明人： Vijay P. Adusumilli , Nicola Telecco
IPC分类号： G11C29/24
CPC分类号： G11C29/846
摘要： Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects receipt of a defective address from the FLASH memory and stores in a redundant shift register redundant data that is downloaded from the FLASH memory chip. The redundant data is used to provide correct FLASH memory data to an external user that interfaces with the companion control chip. In a program mode of operation, the companion control chip provides redundant bits that are stored in redundant columns in the FLASH memory chip. The companion control chip provides flexibility by readily providing a number of different redundancy schemes for bits, nibbles, or bytes without requiring additional logic circuits in the FLASH memory chip itself. Data is transferred between the FLASH memory chip and the companion control chip a byte at a time.
摘要翻译：使用单独的伴随控制器芯片在闪存芯片的外部提供列冗余。伴随芯片最初接收并存储来自FLASH存储器芯片的熔丝地址信息用于闪速存储器中的有缺陷的存储单元。在读取操作模式中，伴随控制芯片检测从FLASH存储器接收到缺陷地址，并存储在从闪速存储器芯片下载的冗余移位寄存器冗余数据中。冗余数据用于向与配套控制芯片接口的外部用户提供正确的FLASH存储器数据。在程序操作模式中，伴随控制芯片提供存储在闪速存储器芯片中的冗余列中的冗余位。伴随的控制芯片通过容易地为位，半字节或字节提供多种不同的冗余方案来提供灵活性，而不需要FLASH存储器芯片本身中的附加逻辑电路。数据在闪存存储器芯片和伴随控制芯片之间一个字节一次传输。

14. 发明申请

US20070014140A1 Nonvolatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US20070014140A1
公开(公告)日：2007-01-18
申请号：US11182374
申请日：2005-07-15
申请人： Nicola Telecco , Vijay Adusumilli , Anil Gupta , Edward Hui , Steven Schumann
发明人： Nicola Telecco , Vijay Adusumilli , Anil Gupta , Edward Hui , Steven Schumann
IPC分类号： G11C5/06
CPC分类号： G11C7/10 , H01L2224/05553 , H01L2224/48137 , H01L2224/49175
摘要： A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.
摘要翻译：非易失性存储装置包括单独的控制器电路和存储器电路。控制器电路制造在第一集成电路芯片上。控制器电路包括多个电荷泵电路，系统接口逻辑电路，存储器控制逻辑电路和一个或多个模拟电路。存储器电路制造在第二集成电路芯片上，并且包括列解码器，行解码器，控制寄存器和数据寄存器。存储器控制器接口区域包括第一集成电路芯片上的第一多个管芯接合焊盘和第二集成电路芯片上的第二多个管芯接合焊盘，使得第一和第二集成电路芯片可以芯片结合在一起。单个控制器电路可以与多个存储器电路接口，从而进一步降低总体成本，因为每个存储器电路不需要专用控制器电路。

15. 发明申请

US20070008775A1 MEMORY ARCHITECTURE WITH ENHANCED OVER-ERASE TOLERANT CONTROL GATE SCHEME 有权
标题翻译：具有增强的易擦除控制门控方案的存储器架构
公开(公告)号：US20070008775A1
公开(公告)日：2007-01-11
申请号：US11178965
申请日：2005-07-11
申请人： Nicola Telecco , Victor Nguyen
发明人： Nicola Telecco , Victor Nguyen
IPC分类号： G11C11/34
CPC分类号： G11C16/3468 , G11C16/26 , G11C16/3477
摘要： The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells. When a memory cell is read, a read voltage is applied to at least one target memory cell, and a negative bias voltage that is lower than a threshold voltage of an over-erased memory cell is also applied to at least one other selected memory cell that is in the same row as the target memory cell. Applying a negative bias voltage to adjacent or proximate memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.
摘要翻译：本发明涉及半导体存储器，特别涉及一种减少过度擦除的存储单元的影响或容忍的非易失性或闪速存储器和方法。当存储单元被读取时，读取电压被施加到至少一个目标存储单元，并且低于过擦除存储单元的阈值电压的负偏置电压也被施加到至少一个其他选择的存储单元它与目标存储单元处于同一行。对相邻或邻近的存储器单元施加负偏置电压会关闭附近的单元，以隔离在读取，编程或擦除操作期间来自过擦除的存储单元的电流。

16. 发明申请

US20060186869A1 Dual stage voltage regulation circuit 有权
标题翻译：双级电压调节电路
公开(公告)号：US20060186869A1
公开(公告)日：2006-08-24
申请号：US11402730
申请日：2006-04-12
申请人： Nicola Telecco
发明人： Nicola Telecco
IPC分类号： G05F1/40 , G05F1/618
CPC分类号： G05F1/465
摘要： A voltage regulator for supplying two types of loads on a common chip, namely a high current load and a low current load. The voltage regulator employs a feedback loop to supply the low current load with a fine degree of regulation and a feed forward arrangement to supply the high current load with a coarse degree of regulation. The feedback loop employs a bandgap reference source feeding a comparator, with an output driver transistor drawing current from a common supply and having an output electrode connected to a voltage divider, allowing a sample of the output to be fed back to the comparator to maintain the desired output voltage. The output electrode also feeds a control transistor for the feed forward arrangement that also draws current from the common supply and supplies the high current load directly. An example of a single chip circuit employing the present invention is a charge pump where the high current load is a series of large capacitors used to multiply charge to produce a high voltage and the low current load is a plurality of clock circuits that apply timing pulses to switches for proper phasing of the capacitors and associated switches to achieve the desired high voltage.
摘要翻译：用于在公共芯片上提供两种类型负载的电压调节器，即高电流负载和低电流负载。电压调节器采用反馈回路来为低电流负载提供精细的调节程度和前馈布置，以提供粗调节的高电流负载。反馈回路采用馈送比较器的带隙参考源，输出驱动晶体管从公共电源抽取电流，并且具有连接到分压器的输出电极，允许将输出的采样反馈到比较器以保持所需输出电压。输出电极还馈送用于前馈布置的控制晶体管，其也从公共电源吸取电流并直接提供高电流负载。采用本发明的单芯片电路的例子是电荷泵，其中高电流负载是用于乘以电荷以产生高电压的一系列大电容器，并且低电流负载是施加定时脉冲的多个时钟电路以切换电容器和相关开关的适当定相以实现期望的高电压。

17. 发明授权

US5986921A Clock circuit for reading a multilevel non volatile memory cells device 失效
标题翻译：用于读取多级非易失性存储单元器件的时钟电路
公开(公告)号：US5986921A
公开(公告)日：1999-11-16
申请号：US883822
申请日：1997-06-27
申请人： Cristiano Calligaro , Nicola Telecco , Guido Torelli
发明人： Cristiano Calligaro , Nicola Telecco , Guido Torelli
IPC分类号： G11C16/06 , G11C11/56 , G11C16/02 , H03K5/13 , G11C13/00
CPC分类号： H03K5/13 , G11C11/5621 , G11C11/5642 , G11C16/32 , G11C2211/5644
摘要： A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block connected to an input terminal for memory address line transition signals. The delay block drives a counter which feedback controls the discharge through a combinational logic circuit connected to the output terminal of the programmable delay block. A logic output circuit, connected to the output terminal of the delay block and to the counter, generates the timing signals.
摘要翻译：一种用于从包括多级非易失性存储器单元的器件读取的定时电路，该电路包括连接到用于存储器地址线转换信号的输入端的单个可编程延迟块。延迟块驱动计数器，其反馈通过连接到可编程延迟块的输出端的组合逻辑电路来控制放电。连接到延迟块的输出端和计数器的逻辑输出电路产生定时信号。

18. 发明申请

US20080005416A1 DATA REGISTER WITH EFFICIENT ERASE, PROGRAM VERIFY, AND DIRECT BIT-LINE MEMORY ACCESS FEATURES 有权
标题翻译：具有有效擦除，程序验证和直接位线记忆访问功能的数据寄存器
公开(公告)号：US20080005416A1
公开(公告)日：2008-01-03
申请号：US11422960
申请日：2006-06-08
申请人： Nicola Telecco
发明人： Nicola Telecco
IPC分类号： G06F13/38
CPC分类号： G06F13/28 , G11C16/3436
摘要： A programmable memory device circuit comprising a sense and programming circuit, a latch circuit, a verify circuit for coupling the latch circuit logic value to a shared indicator line, and a direct memory access circuit coupled to the verify circuit. The DMA circuit couples a bit line to the verify circuit, and the verify circuit couples the direct memory access circuit to a shared verify indicator and DMA line.
摘要翻译：一种可编程存储器件电路，包括感测和编程电路，锁存电路，用于将锁存电路逻辑值耦合到共享指示线的验证电路，以及耦合到验证电路的直接存储器存取电路。 DMA电路将位线耦合到验证电路，并且验证电路将直接存储器访问电路耦合到共享验证指示符和DMA线。

19. 发明授权

US07064529B2 Dual stage voltage regulation circuit 失效
公开(公告)号：US07064529B2
公开(公告)日：2006-06-20
申请号：US10666324
申请日：2003-09-17
申请人： Nicola Telecco
发明人： Nicola Telecco
IPC分类号： G05F1/577
CPC分类号： G05F1/465
摘要： A voltage regulator for supplying two types of loads on a common chip, namely a high current load and a low current load. The voltage regulator employs a feedback loop to supply the low current load with a fine degree of regulation and a feed forward arrangement to supply the high current load with a coarse degree of regulation. The feedback loop employs a bandgap reference source feeding a comparator, with an output driver transistor drawing current from a common supply and having an output electrode connected to a voltage divider, allowing a sample of the output to be fed back to the comparator to maintain the desired output voltage. The output electrode also feeds a control transistor for the feed forward arrangement that also draws current from the common supply and supplies the high current load directly. An example of a single chip circuit employing the present invention is a charge pump where the high current load is a series of large capacitors used to multiply charge to produce a high voltage and the low current load is a plurality of clock circuits that apply timing pulses to switches for proper phasing of the capacitors and associated switches to achieve the desired high voltage.

20. 发明授权

US07031211B1 Direct memory access interface in integrated circuits 失效
标题翻译：集成电路中的直接存储器访问接口
公开(公告)号：US07031211B1
公开(公告)日：2006-04-18
申请号：US10962293
申请日：2004-10-08
申请人： Nicola Telecco , Vijaya P. Adusumilli
发明人： Nicola Telecco , Vijaya P. Adusumilli
IPC分类号： G11C29/00
CPC分类号： G11C29/1201 , G11C29/48 , G11C2029/1204 , G11C2029/5002
摘要： A direct memory access interface incorporates setting bit line selection data into a particular storage element of a desired page register element. The selection data and an access enable signal activate a memory access gate to electrically couple a memory access line with a desired memory bit line. Individual bit lines are selectable independently and more than one page register element may be selected at a time. Direct access of a memory bit line allows measurement and characterization operations to be carried out electrically with selected memory cells. This direct electrical access allows instrumentation to make voltage and current measurements necessary for characterization operations. Area that would otherwise be incorporated for an address decoder gate at each bit line selector circuit is saved since no on-chip decoding scheme is necessary. Additional area savings are realized since selection data storage are within a bidirectional storage element already present in a page register element.
摘要翻译：直接存储器访问接口将设置位线选择数据合并到期望页寄存器元件的特定存储元件中。选择数据和访问使能信号激活存储器访问门以将存储器访问线与期望的存储器位线电耦合。单独的位线可独立选择，并且可以一次选择多于一个的页寄存器元件。存储器位线的直接访问允许测量和表征操作与选择的存储单元电气执行。这种直接电气访问允许仪器进行表征操作所需的电压和电流测量。因为不需要片上解码方案，否则将在每个位线选择器电路处为地址解码器门并入的区域被保存。由于选择数据存储在已经存在于页寄存器元件中的双向存储元件内，所以实现了额外的面积节省。

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