专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20050077955A1 Low-pass filter for a pll, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：低通滤波器，用于pll，锁相环和半导体集成电路
公开(公告)号：US20050077955A1
公开(公告)日：2005-04-14
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03H11/12 , H03H11/04 , H03L7/08 , H03L7/081 , H03L7/089 , H03L7/093 , H03L7/107 , H03B1/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

12. 发明授权

US06603219B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06603219B2
公开(公告)日：2003-08-05
申请号：US09801472
申请日：2001-03-08
申请人： Masaomi Toyama , Shiro Dosho , Naoshi Yanagisawa
发明人： Masaomi Toyama , Shiro Dosho , Naoshi Yanagisawa
IPC分类号： H02J100
CPC分类号： H03K17/005 , H01L24/06 , H01L2224/05554 , H01L2224/49175 , H01L2924/14 , H03K3/03 , H03K17/693 , Y10T307/391 , Y10T307/461 , Y10T307/492 , H01L2924/00
摘要： A semiconductor integrated circuit includes a plurality of units. Each of the units includes a power supply pad, a function circuit, and a power supply control circuit. The plurality of units each have a first state in which the function circuit is in an operating state by the power supply pad being at a prescribed operating potential and a second state in which the function circuit is in a non-operating state by the power supply pad being at a prescribed non-operating potential. The power supply control circuit includes a switching circuit for connecting the power supply pad to the prescribed non-operating potential. The power supply control circuit in each of the plurality of units closes the switching circuit when at least one of the other units is in the first state and opens the switching circuit otherwise.
摘要翻译：半导体集成电路包括多个单元。每个单元包括电源焊盘，功能电路和电源控制电路。所述多个单元各自具有第一状态，其中所述功能电路处于处于规定操作电位的所述功率电路处于工作状态，以及所述功能电路通过所述电源处于非工作状态的第二状态垫处于规定的非操作电位。电源控制电路包括用于将电源焊盘连接到规定的非工作电位的开关电路。当多个单元中的至少一个处于第一状态时，多个单元中的每个单元中的电源控制电路闭合开关电路，否则打开开关电路。

13. 发明申请

US20050049809A1 Analog circuit automatic calibration system 有权
标题翻译：模拟电路自动校准系统
公开(公告)号：US20050049809A1
公开(公告)日：2005-03-03
申请号：US10915345
申请日：2004-08-11
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： G01R31/316 , G01R35/00 , G06F19/00
CPC分类号： G01R35/005 , G01R31/316
摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.
摘要翻译：一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。

14. 发明授权

US5822236A Analog FIFO memory and switching device having a reset operation 失效
标题翻译：具有复位操作的模拟FIFO存储器和开关器件
公开(公告)号：US5822236A
公开(公告)日：1998-10-13
申请号：US863209
申请日：1997-05-27
申请人： Shiro Dosho , Hidehiko Kurimoto , Naoshi Yanagisawa
发明人： Shiro Dosho , Hidehiko Kurimoto , Naoshi Yanagisawa
IPC分类号： G11C27/00 , G11C27/04 , H03H19/00 , H04N9/78
CPC分类号： G11C27/04 , G11C27/00 , H03H19/004 , H04N9/78
摘要： The invention provides an analog FIFO memory from which a written analog signal can be accurately read by eliminating errors in the analog signal between the write operation and the read operation. Prior to the read operation for reading the analog signal from a memory cell through a memory bus, a reset operation for setting the memory bus at a predetermined potential is conducted so as to remove a charge stored in a parasitic capacitance of the memory bus. The input terminal of a read circuit is set at a predetermined potential, with a write circuit disconnected from the memory bus by using an input circuit and with the read circuit connected with the memory bus by using an output circuit. In this manner, the memory bus is set at the predetermined potential, and the charge stored in the parasitic capacitance is discharged. At this point, a switch in each memory cell is in an off-state, and hence, a charge corresponding to the analog signal can be retained in the memory cell.
摘要翻译：本发明提供了一种模拟FIFO存储器，通过消除写入操作和读取操作之间的模拟信号中的错误，可以准确地读取写入的模拟信号。在从存储器单元通过存储器总线读取模拟信号的读取操作之前，进行用于将存储器总线设置在预定电位的复位操作，以便消除存储在存储器总线的寄生电容中的电荷。读取电路的输入端子通过使用输入电路和与存储器总线连接的读取电路通过使用输出电路将写入电路从存储器总线断开而被设置在预定电位。以这种方式，将存储器总线设置在预定电位，并且存储在寄生电容中的电荷被放电。此时，每个存储单元中的开关处于截止状态，因此可以将与模拟信号相对应的电荷保留在存储单元中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式