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11. 发明申请

US20070166979A1 METAL ETCHING PROCESS AND REWORK METHOD THEREOF 有权
标题翻译：金属蚀刻工艺及其制作方法
公开(公告)号：US20070166979A1
公开(公告)日：2007-07-19
申请号：US11307801
申请日：2006-02-23
申请人： Tza-Hao Wang , Jin-Yang Huang , Hung-Kwei Liao , Ming-Sheng Tung
发明人： Tza-Hao Wang , Jin-Yang Huang , Hung-Kwei Liao , Ming-Sheng Tung
IPC分类号： H01L21/44
CPC分类号： H01L21/32139 , H01L21/321 , H01L21/32135
摘要： A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.
摘要翻译：描述金属蚀刻工艺。提供其上具有介电层的基板。在电介质层上形成铝 - 铜合金层。在铝 - 铜合金层上形成硬掩模层。在硬掩模层上形成图案化的光致抗蚀剂层，然后对硬掩模层进行图案化。进行热处理工艺。热处理过程在大于300℃的温度下进行至少3分钟的时间。此后，使用图案化的硬掩模层作为蚀刻掩模蚀刻铝 - 铜合金层。由于热处理，铝 - 铜合金层内的金属沉淀物（CuAl 2 N 2）被消除，因此改善了金属蚀刻工艺。

12. 发明申请

US20060128157A1 Semiconductor structure with partially etched gate and method of fabricating the same 审中-公开
标题翻译：具有部分蚀刻栅极的半导体结构及其制造方法
公开(公告)号：US20060128157A1
公开(公告)日：2006-06-15
申请号：US11338679
申请日：2006-01-25
申请人： Yueh-Chuan Lee , Ming-Sheng Tung
发明人： Yueh-Chuan Lee , Ming-Sheng Tung
IPC分类号： H01L21/311 , H01L21/461 , H01L21/302
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28061 , H01L21/28114 , H01L21/823425 , H01L21/823456 , H01L29/42376
摘要： A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.
摘要翻译：具有部分蚀刻栅极的半导体结构及其制造方法。具有单面或双面部分蚀刻栅极的半导体结构包括依次层叠在衬底上以形成栅极结构的栅介质层，栅极导电层和覆盖层，以及设置在栅极侧壁上的衬层结构，其中衬里层被部分蚀刻以暴露相邻的栅极结构。此外，层间电介质层覆盖栅极结构，并且在层间电介质层中形成接触，将衬底和栅极结构的一部分暴露于其中，其中栅极结构的暴露部分的衬层被部分删除。

13. 发明申请

US20070093014A1 Method for preventing doped boron in a dielectric layer from diffusing into a substrate 审中-公开
标题翻译：用于防止介电层中的掺杂硼扩散到衬底中的方法
公开(公告)号：US20070093014A1
公开(公告)日：2007-04-26
申请号：US11258115
申请日：2005-10-26
申请人： Chia-Shun Hsiao , Ming-Sheng Tung , Hong-Ming Chen , Ching-Hsien Huang
发明人： Chia-Shun Hsiao , Ming-Sheng Tung , Hong-Ming Chen , Ching-Hsien Huang
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L27/105 , H01L21/823456 , H01L27/1052
摘要： The present invention provides a method for preventing doped boron in a dielectric layer from diffusing into a substrate. First, at least one gate is formed on a periphery circuit area and a memory array area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. Then, a barrier layer is formed on the memory array area and the periphery circuit area, and an undoped oxide barrier is formed on the periphery circuit area. Finally, a silicate glass containing boron is deposited on the memory array area and the periphery circuit area.
摘要翻译：本发明提供一种防止介电层中的掺杂硼扩散到衬底中的方法。首先，分别在基板的外围电路区域和存储器阵列区域上形成至少一个栅极，其中存储器阵列区域中的图案密度高于外围电路区域中的图案密度。然后，在存储器阵列区域和外围电路区域上形成阻挡层，并且在外围电路区域上形成未掺杂的氧化物屏障。最后，将含硼的硅酸盐玻璃沉积在存储器阵列区域和外围电路区域上。

14. 发明授权

US07034354B2 Semiconductor structure with lining layer partially etched on sidewall of the gate 有权
标题翻译：具有在栅极侧壁部分蚀刻的衬层的半导体结构
公开(公告)号：US07034354B2
公开(公告)日：2006-04-25
申请号：US10695739
申请日：2003-10-30
申请人： Yueh-Chuan Lee , Ming-Sheng Tung
发明人： Yueh-Chuan Lee , Ming-Sheng Tung
IPC分类号： H01L21/108
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28061 , H01L21/28114 , H01L21/823425 , H01L21/823456 , H01L29/42376
摘要： A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.
摘要翻译：具有部分蚀刻栅极的半导体结构及其制造方法。具有单面或双面部分蚀刻栅极的半导体结构包括依次层叠在衬底上以形成栅极结构的栅介质层，栅极导电层和覆盖层，以及设置在栅极侧壁上的衬层结构，其中衬里层被部分蚀刻以暴露相邻的栅极结构。此外，层间电介质层覆盖栅极结构，并且在层间电介质层中形成接触，将衬底和栅极结构的一部分暴露于其中，其中栅极结构的暴露部分的衬层被部分删除。

15. 发明申请

US20050127453A1 Method of forming self-aligned contact structure with locally etched gate conductive layer 审中-公开
标题翻译：用局部蚀刻的栅极导电层形成自对准接触结构的方法
公开(公告)号：US20050127453A1
公开(公告)日：2005-06-16
申请号：US11041503
申请日：2005-01-21
申请人： Ming-Sheng Tung , Yueh-Chuan Lee
发明人： Ming-Sheng Tung , Yueh-Chuan Lee
IPC分类号： H01L21/336 , H01L21/60 , H01L23/485 , H01L21/8242 , H01L31/062 , H01L31/113
CPC分类号： H01L21/76897 , H01L23/485 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.
摘要翻译：用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。

16. 发明申请

US20050106844A1 Method of fabricating a MOSFET device 审中-公开
标题翻译：制造MOSFET器件的方法
公开(公告)号：US20050106844A1
公开(公告)日：2005-05-19
申请号：US10788807
申请日：2004-02-27
申请人： Ming-Sheng Tung , Yueh-Chuan Lee , Fang-Yu Yeh , Chi Lin
发明人： Ming-Sheng Tung , Yueh-Chuan Lee , Fang-Yu Yeh , Chi Lin
IPC分类号： H01L21/336 , H01L29/10
CPC分类号： H01L29/6653 , H01L29/1045 , H01L29/6659 , H01L29/66659
摘要： Ions are implanted into a substrate, using a gate and its sidewall liner on the substrate as the mask, to form a source/drain region in the substrate beneath the liner and adjacent to the two sides of the gate. The liner is etched to reduce its thickness. Then, ions are implanted into the substrate to form a halo doped region surrounding the source/drain region. The halo doped region is closer to the MOSFET channel region and overlaps less with the source/drain region. Therefore, the device threshold voltage can be sustained and the junction leakage can also be minimized.
摘要翻译：将离子以植入基板上的栅极及其侧壁衬垫作为掩模注入到衬底中，以在衬底下面形成源极/漏极区域，并且邻近栅极的两侧。蚀刻衬里以减小其厚度。然后，将离子注入到衬底中以形成围绕源/漏区的卤素掺杂区。卤素掺杂区域更靠近MOSFET沟道区域，并且与源极/漏极区域重叠较小。因此，可以维持器件阈值电压，也可以最小化结漏电。

17. 发明授权

US06855610B2 Method of forming self-aligned contact structure with locally etched gate conductive layer 有权
标题翻译：用局部蚀刻的栅极导电层形成自对准接触结构的方法
公开(公告)号：US06855610B2
公开(公告)日：2005-02-15
申请号：US10330522
申请日：2002-12-27
申请人： Ming-Sheng Tung , Yueh-Chuan Lee
发明人： Ming-Sheng Tung , Yueh-Chuan Lee
IPC分类号： H01L21/336 , H01L21/60 , H01L23/485
CPC分类号： H01L21/76897 , H01L23/485 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.
摘要翻译：用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。

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