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11. 发明授权

US09146846B2 Programmable physical address mapping for memory 有权
标题翻译：存储器的可编程物理地址映射
公开(公告)号：US09146846B2
公开(公告)日：2015-09-29
申请号：US13617673
申请日：2012-09-14
申请人： Gabriel H. Loh , Mauricio Breternitz, Jr.
发明人： Gabriel H. Loh , Mauricio Breternitz, Jr.
IPC分类号： G06F12/06 , G06F12/00 , G06F12/02
CPC分类号： G06F12/00 , G06F12/0207 , G06F12/0653 , G06F2212/1016
摘要： A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.
摘要翻译：存储器实现可编程物理地址映射，可以改变以反映对存储器的观察或预期的改变的存储器访问模式。存储器采用地址解码逻辑，其可以实现物理地址和相应存储器位置之间的各种物理地址映射中的任何一种。物理地址映射可以将数据定位在存储器的一个或多个存储体和行中，以便于给定访问模式更有效的存储器访问。存储器的硬件采用的可编程物理地址映射可以包括但不限于硬连线逻辑门，可编程查找表或其它映射表，可重构逻辑或其组合。物理地址映射可以针对整个存储器或基于每存储器区域编程。

12. 发明申请

US20140372782A1 COMBINED DYNAMIC AND STATIC POWER AND PERFORMANCE OPTIMIZATION ON DATA CENTERS 有权
标题翻译：数据中心的组合动态和静态功能和性能优化
公开(公告)号：US20140372782A1
公开(公告)日：2014-12-18
申请号：US13917417
申请日：2013-06-13
申请人： Mauricio Breternitz , Leonardo Piga , Patryk Kaminski
发明人： Mauricio Breternitz , Leonardo Piga , Patryk Kaminski
IPC分类号： G06F1/28
CPC分类号： G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126
摘要： Various datacenter or other computing center control apparatus and methods are disclosed. In one aspect, a method of computing is provided that includes defining plural processor performance bins where each processor performance bin has a processor performance state. At least one processor is assigned to each of the plural processor performance bins. Processor performance metrics of at least one of the processors are monitored while the at least one of the processors executes an incoming task. Processor power is modeled based on the monitored performance metrics. Future incoming tasks are assigned to one of the processor performance bins based on the modeled processor power.
摘要翻译：公开了各种数据中心或其他计算中心控制装置和方法。在一个方面，提供了一种计算方法，其包括定义多个处理器性能箱，其中每个处理器性能仓具有处理器性能状态。至少一个处理器分配给多个处理器性能仓中的每一个。在处理器中的至少一个处理器执行传入任务时，监视至少一个处理器的处理器性能度量。处理器电源是基于监视的性能指标进行建模的。基于建模的处理器功率，将来的进入任务分配给一个处理器性能箱。

13. 发明申请

US20110320775A1 ACCELERATING EXECUTION OF COMPRESSED CODE 审中-公开
标题翻译：加快执行压缩码
公开(公告)号：US20110320775A1
公开(公告)日：2011-12-29
申请号：US12824187
申请日：2010-06-27
申请人： Edson Borin , Mauricio Breternitz, JR. , Nir Bone , Shlomo Avni
发明人： Edson Borin , Mauricio Breternitz, JR. , Nir Bone , Shlomo Avni
IPC分类号： G06F9/34 , G06F9/40
CPC分类号： H03M7/30 , G06F9/30145 , G06F9/30178 , G06F9/382 , G06F9/445 , Y02D10/43
摘要： Methods and apparatus relating to accelerating execution of compressed code are described. In one embodiment, a two-level embedded code decompression scheme is utilized which eliminates bubbles, which may increase speed and/or reduce power consumption. Other embodiments are also described and claimed.
摘要翻译：描述与加速压缩代码执行有关的方法和装置。在一个实施例中，利用消除气泡的两级嵌入式代码解压缩方案，这可以增加速度和/或降低功耗。还描述和要求保护其他实施例。

14. 发明授权

US07757221B2 Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints 有权
标题翻译：用于动态二进制转换器的装置和方法，以最小的优化约束来支持精确异常
公开(公告)号：US07757221B2
公开(公告)日：2010-07-13
申请号：US11241610
申请日：2005-09-30
申请人： Bixia Zheng , Cheng C. Wang , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
发明人： Bixia Zheng , Cheng C. Wang , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F9/45516 , G06F8/443
摘要： A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.
摘要翻译：一种用于动态二进制转换器的方法和装置，以最小的优化约束来支持精确的异常。在一个实施例中，该方法包括将源指令集架构（ISA）生成的源二进制应用程序转换为源二进制应用程序的顺序中间表示（IR）。在一个实施例中，顺序IR被修改为包含从源二进制应用程序识别的每个异常指令的异常恢复信息，以使动态二进制转换器（DBT）能够将异常恢复值表示为由IR指令使用的常规值。在一个实施例中，可以对异常指令向下移动通过不可逆指令以形成非顺序IR的限制来优化顺序IR。在一个实施例中，非顺序IR被优化以形成目标ISA的翻译二进制应用程序。描述和要求保护其他实施例。

15. 发明申请

US20090172713A1 ON-DEMAND EMULATION VIA USER-LEVEL EXCEPTION HANDLING 有权
标题翻译：通过用户级别异常处理实现仿真
公开(公告)号：US20090172713A1
公开(公告)日：2009-07-02
申请号：US11968055
申请日：2007-12-31
申请人： Ho-Seop Kim , Mauricio Breternitz, JR. , Youfeng Wu
发明人： Ho-Seop Kim , Mauricio Breternitz, JR. , Youfeng Wu
IPC分类号： G06F9/54 , G06F9/302
CPC分类号： G06F9/30145 , G06F9/4552
摘要： Methods and apparatuses enable on-demand instruction emulation via user-level exception handling. A non-supported instruction triggers an exception during runtime of a program. In response to the exception, a user-level or application-level exception handler is launched, instead of a kernel-level handler. Then the exception handler can execute at the application layer instead of the kernel level. The handler identifies the instruction and emulates the instruction, where emulation of the instruction is supported by the handler. Emulating the instructions enables the program to continue execution. Repeated instruction emulation is amortized via dynamic binary translation of hot code.
摘要翻译：方法和设备通过用户级异常处理实现按需指令仿真。不支持的指令在程序运行时触发异常。响应于异常，启动用户级或应用程序级异常处理程序，而不是内核级处理程序。然后异常处理程序可以在应用程序层而不是内核级别执行。处理程序标识指令并模拟指令，其中指令的仿真由处理程序支持。仿真指令使程序能够继续执行。重复的指令仿真通过热代码的动态二进制转换进行分摊。

16. 发明授权

US07430574B2 Efficient execution and emulation of bit scan operations 有权
标题翻译：位扫描操作的高效执行和仿真
公开(公告)号：US07430574B2
公开(公告)日：2008-09-30
申请号：US10877931
申请日：2004-06-24
申请人： Mauricio Breternitz, Jr. , Youfeng Wu , Tal Abir
发明人： Mauricio Breternitz, Jr. , Youfeng Wu , Tal Abir
IPC分类号： G06F7/00
CPC分类号： G06F7/74
摘要： Methods are disclosed to implement bit scan operations using properties of two's complement arithmetic and compute zero index instructions. A data value may be provided and the most-significant or least-significant bit may be determined using the methods set forth herein.
摘要翻译：公开了使用二进制补码运算和计算零索引指令的特性实现位扫描操作的方法。可以提供数据值，并且可以使用本文所阐述的方法来确定最高有效位或最低有效位。

17. 发明申请

US20070079304A1 Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints 有权
标题翻译：用于动态二进制转换器的装置和方法，以最小的优化约束来支持精确异常
公开(公告)号：US20070079304A1
公开(公告)日：2007-04-05
申请号：US11241610
申请日：2005-09-30
申请人： Bixia Zheng , Cheng Wang , Ho-seop Kim , Mauricio Breternitz , Youfeng Wu
发明人： Bixia Zheng , Cheng Wang , Ho-seop Kim , Mauricio Breternitz , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F9/45516 , G06F8/443
摘要： A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.
摘要翻译：一种用于动态二进制转换器的方法和装置，以最小的优化约束来支持精确的异常。在一个实施例中，该方法包括将源指令集架构（ISA）生成的源二进制应用程序转换为源二进制应用程序的顺序中间表示（IR）。在一个实施例中，顺序IR被修改为包含从源二进制应用程序识别的每个异常指令的异常恢复信息，以使动态二进制转换器（DBT）能够将异常恢复值表示为由IR指令使用的常规值。在一个实施例中，可以对异常指令向下移动通过不可逆指令以形成非顺序IR的限制来优化顺序IR。在一个实施例中，非顺序IR被优化以形成目标ISA的翻译二进制应用程序。描述和要求保护其他实施例。

18. 发明授权

US06523095B1 Method and data processing system for using quick decode instructions 失效
标题翻译：使用快速解码指令的方法和数据处理系统
公开(公告)号：US06523095B1
公开(公告)日：2003-02-18
申请号：US08684717
申请日：1996-07-22
申请人： Mauricio Breternitz, Jr.
发明人： Mauricio Breternitz, Jr.
IPC分类号： G06F1200
CPC分类号： G06F9/3812 , G06F9/30174 , G06F9/30185 , G06F12/0875
摘要： A cache line of a cache (230) contains a modifiable instruction. The modifiable instruction is decoded by a central processor unit (210) (CPU) which performs the function associated with the modifiable instruction. After the modifiable instruction has been executed, the CPU (210) sets an instruction modified bit associated with the cache (200) based on the execution results of the modifiable instruction. During a subsequent process of the modifiable instruction location, the CPU Decode Unit (212) substitutes a modified instruction for the modifiable instruction based on the instruction modify indicator.
摘要翻译：高速缓存（230）的高速缓存行包含可修改的指令。可修改的指令由执行与可修改指令相关联的功能的中央处理器单元（210）（CPU）解码。在执行可修改指令之后，CPU（210）基于可修改指令的执行结果设置与高速缓存（200）相关联的指令修改位。在可修改指令位置的后续处理期间，CPU解码单元（212）基于指令修改指示符替换修改的指令用于可修改指令。

19. 发明授权

US06484228B2 Method and apparatus for data compression and decompression for a data processor system 失效
标题翻译：用于数据处理器系统的数据压缩和解压缩的方法和装置
公开(公告)号：US06484228B2
公开(公告)日：2002-11-19
申请号：US10008074
申请日：2001-11-05
申请人： Mauricio Breternitz, Jr. , Roger A. Smith
发明人： Mauricio Breternitz, Jr. , Roger A. Smith
IPC分类号： G06F1200
CPC分类号： G06F9/3802 , G06F9/3017 , G06F12/0875 , G06F2212/401
摘要： During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.
摘要翻译：在压缩部分期间，存储器（20）被分成高速缓存行块（500）。通过用压缩地址目的地替换地址间接指令的地址目的地来对每个高速缓存行块进行压缩和修改。每个高速缓存行块被修改为具有流间接指令作为每个高速缓存行中的最后一条指令。压缩高速缓存行块（500）被存储在存储器（858）中。在解压缩部分期间，基于指令指针（902）值来访问高速缓存行（500）。缓存行被解压缩并存储在缓存中。基于指令指针（902）的值确定缓存标签。

20. 发明授权

US09152532B2 System and method for configuring a cloud computing system with a synthetic test workload 有权
标题翻译：用于配置具有合成测试工作负载的云计算系统的系统和方法
公开(公告)号：US09152532B2
公开(公告)日：2015-10-06
申请号：US13568459
申请日：2012-08-07
申请人： Mauricio Breternitz , Keith A. Lowery , Patryk Kaminski , Anton Chernoff
发明人： Mauricio Breternitz , Keith A. Lowery , Patryk Kaminski , Anton Chernoff
IPC分类号： G06F11/00 , G06F11/34 , G06F11/26 , G06F9/50
CPC分类号： G06F11/3495 , G06F9/5072 , G06F11/26 , G06F11/3414 , G06F11/3433
摘要： The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes selecting, based on a user selection received via a user interface, a workload for execution on a cluster of nodes of the computing system. The workload is selected from a plurality of available workloads including an actual workload and a synthetic test workload. The method further includes configuring the cluster of nodes of the computing system to execute the selected workload such that processing of the selected workload is distributed across the cluster of nodes. The synthetic test workload may be generated by a code synthesizer based on a set of user-defined workload parameters provided via a user interface that identify execution characteristics of the synthetic test workload.
摘要翻译：本公开涉及用于配置诸如云计算系统之类的计算系统的方法和系统。一种方法包括：基于经由用户接口接收到的用户选择来选择用于在所述计算系统的节点簇上执行的工作负载。从多个可用工作负载中选择工作负载，包括实际工作负载和合成测试工作负载。该方法还包括配置计算系统的节点集群以执行所选择的工作负载，使得所选择的工作负载的处理分布在节点簇上。综合测试工作量可以由代码合成器基于经由识别合成测试工作负载的执行特性的用户界面提供的一组用户定义的工作负载参数来生成。

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