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11. 发明申请

US20070286221A1 Memory management method and memory architecture for transmitting UWB PCA frames 审中-公开
标题翻译：用于传输UWB PCA帧的内存管理方法和存储器架构
公开(公告)号：US20070286221A1
公开(公告)日：2007-12-13
申请号：US11452791
申请日：2006-06-13
申请人： Mau-Lin Wu , Tung-Hui Lee , Chieh-Hua Chen , Hsin-Pu Chung , Youn-Tai Lee
发明人： Mau-Lin Wu , Tung-Hui Lee , Chieh-Hua Chen , Hsin-Pu Chung , Youn-Tai Lee
IPC分类号： H04L12/56 , H04J3/02
CPC分类号： H04L12/403
摘要： A memory management method and a memory architecture for transmitting ultra-wideband (UWB) prioritized channel access (PCA) frames are provided. The method comprises the steps of assigning a pre-load queue to each of a plurality of access categories for storing UWB PCA frames to be transmitted, and, when one of the access categories gains transmission opportunity (TXOP), assigning a common area queue to that access category for storing UWB PCA frames to be transmitted. Moreover, when a UWB PCA frame in one of the pre-load queues reaches a predetermined size, the access category corresponding to the pre-load queue starts its backoff state machine in order to gain the TXOP.
摘要翻译：提供了用于发送超宽带（UWB）优先信道接入（PCA）帧的存储器管理方法和存储器架构。该方法包括以下步骤：将预加载队列分配给用于存储要发送的UWB PCA帧的多个接入类别中的每一个，并且当其中一个接入类别获得传输机会（TXOP）时，将公共区域队列分配给用于存储要发送的UWB PCA帧的接入类别。此外，当一个预加载队列中的UWB PCA帧达到预定大小时，对应于预加载队列的访问类别启动其退避状态机，以获得TXOP。

12. 发明授权

US06912109B1 Power-rail ESD clamp circuits with well-triggered PMOS 有权
标题翻译：具有良好触发的PMOS的电源轨ESD钳位电路
公开(公告)号：US06912109B1
公开(公告)日：2005-06-28
申请号：US09604067
申请日：2000-06-26
申请人： Ming-Dou Ker , Mau-Lin Wu
发明人： Ming-Dou Ker , Mau-Lin Wu
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0266
摘要： A new ESD (Electrostatic Discharge) protection circuit with well-triggered PMOS is provided for application in power-rail ESD protection. A PMOS device is connected between the VDD and VSS power lines to sustain the ESD overstress current during the time that the ESD voltage is applied between the VDD and the VSS power lines. In deep submicron CMOS p-substrate technology, the weak point of ESD overstress control is typically associated with the NMOS device. For this reason, the invention uses a power-rail ESD clamp circuit that incorporates a PMOS device. Applying gate-coupled and N-well triggering techniques, the PMOS can be turned on more efficiently when the ESD overstress is present between the power lines. For p-substrate CMOS technology, it is difficult to couple a high voltage to the substrate of the NMOS device while high voltage is readily coupled to the N-well of a PMOS device. The proposed ESD clamp circuit can be applied efficiently to protect the ESD overstress between power rails.
摘要翻译：提供了具有良好触发PMOS的新型ESD（静电放电）保护电路，用于电力轨道ESD保护。在VDD和VSS电源线之间施加ESD电压的时间期间，PMOS器件连接在VDD和VSS电源线之间以维持ESD过应力电流。在深亚微米CMOS p衬底技术中，ESD过应力控制的弱点通常与NMOS器件相关。因此，本发明使用包含PMOS器件的电力 - 轨道ESD钳位电路。应用栅极耦合和N阱触发技术，当电源线之间存在ESD过应力时，可以更有效地开启PMOS。对于p衬底CMOS技术，难以将高电压耦合到NMOS器件的衬底，同时高电压容易地耦合到PMOS器件的N阱。提出的ESD钳位电路可以有效地应用于保护电源轨之间的ESD过载。

13. 发明申请

US20070089041A1 DUPLICATE DETECTION CIRCUIT FOR RECEIVER 有权
标题翻译：用于接收器的双重检测电路
公开(公告)号：US20070089041A1
公开(公告)日：2007-04-19
申请号：US11163398
申请日：2005-10-17
申请人： Mau-Lin Wu
发明人： Mau-Lin Wu
IPC分类号： H03M13/00
CPC分类号： H04L1/0045 , H03M13/09 , H04L1/0052 , H04L1/0061 , H04L1/0072 , H04L1/1829
摘要： A duplicate detection circuit for a receiver includes a CRC generator for generating a CRC value of frame header information, and a control circuit coupled to the CRC generator. The control circuit has a first output, a second output, and a control input. When the control input is not set, the control circuit outputs the CRC value at the first output. When the control input is set, the control circuit outputs the CRC value at the second output. A buffer has an input coupled to the first output of the control circuit. A compare circuit has an input coupled to an output of the buffer and another input coupled to the second output of the control circuit. The compare circuit compares a CRC value at the second output of the control circuit with a CRC value stored in the buffer, and outputs a duplicate indication when detecting a match.
摘要翻译：用于接收机的重复检测电路包括用于产生帧头信息的CRC值的CRC发生器和耦合到CRC发生器的控制电路。控制电路具有第一输出，第二输出和控制输入。当控制输入未设定时，控制电路在第一个输出端输出CRC值。当控制输入被设置时，控制电路在第二个输出端输出CRC值。缓冲器具有耦合到控制电路的第一输出的输入。比较电路具有耦合到缓冲器的输出和耦合到控制电路的第二输出的另一个输入的输入。比较电路将控制电路的第二输出端的CRC值与存储在缓冲器中的CRC值进行比较，并在检测到匹配时输出重复指示。

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