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11. 发明申请

US20050240829A1 Lockstep error signaling 有权
标题翻译：锁步错误信号
公开(公告)号：US20050240829A1
公开(公告)日：2005-10-27
申请号：US10818993
申请日：2004-04-06
申请人： Kevin Safford , Eric Delano
发明人： Kevin Safford , Eric Delano
IPC分类号： G06F11/00 , G06F11/07 , G06F11/16
CPC分类号： G06F11/165 , G06F11/0724 , G06F11/0772 , G06F11/1641 , G06F11/1654 , G06F2201/845
摘要： Techniques are disclosed, for use in a computer system including a plurality of processing units coupled over a system fabric, to identify a lockstep error associated with a first packet to be transmitted over the system fabric; set a viral indicator in the first packet to indicate the lockstep error; and transmit the modified packet over the system fabric.
摘要翻译：公开了用于包括通过系统结构耦合的多个处理单元的计算机系统中的技术，以识别与要在系统结构上传送的第一分组相关联的锁步错误; 在第一个数据包中设置病毒指示符，以指示锁步错误; 并通过系统结构传输修改的数据包。

12. 发明申请

US20130275787A1 Methods And Apparatuses For Reducing Step Loads Of Processors 审中-公开
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US20130275787A1
公开(公告)日：2013-10-17
申请号：US13913864
申请日：2013-06-10
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

13. 发明申请

US20090070607A1 Methods and apparatuses for reducing step loads of processors 有权
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US20090070607A1
公开(公告)日：2009-03-12
申请号：US11900316
申请日：2007-09-11
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

14. 发明申请

US20070061812A1 Method and apparatus for communicating information between lock stepped processors 有权
标题翻译：用于在锁步阶处理器之间传递信息的方法和装置
公开(公告)号：US20070061812A1
公开(公告)日：2007-03-15
申请号：US11598781
申请日：2006-11-14
申请人： Kevin Safford , Jeremy Petsinger
发明人： Kevin Safford , Jeremy Petsinger
IPC分类号： G06F9/46
CPC分类号： G06F11/1683 , G06F9/30189 , G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F11/1641
摘要： An apparatus for communicating between lock step is incorporated on two or more processors operating in a lock step mode. Each of the processors includes processor logic to execute a code sequence, and an identical code sequence is executed by the processor logic. The apparatus further includes a processor-specific resource referenced by the code sequence. A multiplexer is coupled to the processor-specific resource, and is controlled to read data based on the identification. Coupled to the processors is a lock step logic block operable to read and compare the output of each of the processors. The lock step logic determines if operation of the processors is in a lock step mode or in an independent processor mode. Such determination may be made by the lock step logic turning off, for example.
摘要翻译：用于锁定步骤之间的通信的装置被结合在以锁定步骤模式操作的两个或多个处理器上。每个处理器包括执行代码序列的处理器逻辑，并且处理器逻辑执行相同的代码序列。该装置还包括由代码序列引用的特定于处理器的资源。多路复用器耦合到特定于处理器的资源，并被控制以基于识别来读取数据。耦合到处理器的是锁步骤逻辑块，可操作以读取和比较每个处理器的输出。锁定步骤逻辑确定处理器的操作是处于锁定步骤模式还是处于独立处理器模式。例如，可以通过锁定步骤逻辑关闭来进行这种确定。

15. 发明申请

US20060085677A1 Method and apparatus for seeding differences in lock-stepped processors 失效
标题翻译：在锁阶处理器中播种差异的方法和装置
公开(公告)号：US20060085677A1
公开(公告)日：2006-04-20
申请号：US11290504
申请日：2005-12-01
申请人： Kevin Safford , Jeremy Petsinger
发明人： Kevin Safford , Jeremy Petsinger
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F9/52
摘要： An apparatus, and a corresponding method, are used for seeding differences in lock stepped processors, the apparatus implemented on two or more processors operating in a lock step mode. Each of the two or more processors comprise a processor-specific resource operable to seed the differences, a processor logic to execute a code sequence, in which an identical code sequence is executed by the processor logic of each of the two or more processors, and an output to provide a result of execution of the code sequence. The processor outputs, based on execution of the code sequence is provided to a lock step logic operable to read and compare the output of each of the two or more processors.
摘要翻译：一种装置和相应的方法用于锁定步进式处理器的种子差异，该装置在两个或多个处理器上实现，该处理器以锁步骤模式运行。两个或更多个处理器中的每一个包括可操作以对差异进行种子化的处理器专用资源，处理器逻辑以执行代码序列，其中由两个或多个处理器中的每一个的处理器逻辑执行相同的代码序列，以及用于提供执行代码序列的结果的输出。基于代码序列的执行，处理器输出被提供给可操作以读取和比较两个或更多个处理器中的每一个的输出的锁定步骤逻辑。

16. 发明申请

US20050240811A1 Core-level processor lockstepping 有权
标题翻译：核心级处理器锁步
公开(公告)号：US20050240811A1
公开(公告)日：2005-10-27
申请号：US10818975
申请日：2004-04-06
申请人： Kevin Safford , Christopher Lyles , Eric Delano
发明人： Kevin Safford , Christopher Lyles , Eric Delano
IPC分类号： G06F11/18 , G06F11/00 , G06F11/16 , G06F11/20
CPC分类号： G06F11/1679 , G06F11/1641
摘要： A device is provided which includes a first microprocessor core to generate a first output signal; a second microprocessor core to generate a second output signal; a switching fabric having a first input/output port; and lockstep logic, coupled between the first input/output port of the switching fabric and the first and second microprocessor cores, to detect whether the first output signal differs from the second output signal.
摘要翻译：提供一种装置，其包括用于产生第一输出信号的第一微处理器核心; 第二微处理器核心，用于产生第二输出信号; 具有第一输入/输出端口的交换结构; 以及耦合在交换结构的第一输入/输出端口与第一和第二微处理器核心之间的锁步逻辑，以检测第一输出信号是否与第二输出信号不同。

17. 发明申请

US20050240793A1 Architectural support for selective use of high-reliability mode in a computer system 失效
标题翻译：在计算机系统中选择性使用高可靠性模式的架构支持
公开(公告)号：US20050240793A1
公开(公告)日：2005-10-27
申请号：US10819241
申请日：2004-04-06
申请人： Kevin Safford , Donald Soltis
发明人： Kevin Safford , Donald Soltis
IPC分类号： G06F9/30 , G06F11/00
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/30189 , G06F9/3851 , G06F11/1629 , G06F2201/845
摘要： In one aspect of the present invention, a circuit is provided which implements an instruction set architecture defining a first instruction group, a second instruction group to enter a high-reliability mode of operation, and a third instruction group to enter a non-high-reliability mode of operation. The circuit includes means for causing the circuit to enter the high-reliability mode of operation in response to receiving the second instruction group; means for causing the circuit to enter the non-high-reliability mode of operation in response to receiving the third instruction group; first execution means for executing the first instruction group in the high-reliability mode of operation if the circuit is in the high-reliability mode of operation; and second execution means for executing the first instruction group without in the non-high-reliability mode of operation if the circuit is in the non-high-reliability mode of operation.
摘要翻译：在本发明的一个方面，提供一种电路，其实现定义第一指令组的指令集架构，进入高可靠性操作模式的第二指令组，以及进入非高速模式的第三指令组，可靠的运行模式。电路包括用于响应于接收到第二指令组而使电路进入高可靠性操作模式的装置; 响应于接收到第三指令组使电路进入非高可靠性操作模式的装置; 如果电路处于高可靠性操作模式，则在高可靠性操作模式下执行第一指令组的第一执行装置; 以及第二执行装置，用于如果电路处于非高可靠性操作模式，则在不处于非高可靠性操作模式的情况下执行第一指令组。

18. 发明申请

US20050138478A1 Error detection method and system for processors that employ alternating threads 审中-公开
标题翻译：使用交替线程的处理器的错误检测方法和系统
公开(公告)号：US20050138478A1
公开(公告)日：2005-06-23
申请号：US10714258
申请日：2003-11-14
申请人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
发明人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
IPC分类号： G06F11/14 , G06F11/00
CPC分类号： G06F11/1497 , G06F9/3861
摘要： Microprocessor that includes a mechanism for detecting soft errors. The processor includes an instruction fetch unit for fetching an instruction and an instruction decoder for decoding the instruction. The mechanism for detecting soft errors includes duplication hardware for duplicating the instruction and comparison hardware. The processor further includes a first execution unit for executing the instruction in a first execution cycle and the duplicated instruction in a second execution cycle. The comparison hardware compares the results of the first execution cycle and the results of the second execution cycle. The comparison hardware can include an exception unit for generating an exception (e.g., raising a fault) when the results are not the same. The processor also includes a commit unit for committing one of the results when the results are the same.
摘要翻译：微处理器，包括检测软错误的机制。处理器包括用于取出指令的指令获取单元和用于解码指令的指令解码器。用于检测软错误的机制包括用于复制指令和比较硬件的复制硬件。处理器还包括用于在第一执行周期中执行指令的第一执行单元和在第二执行周期中的复制指令。比较硬件比较第一个执行周期的结果和第二个执行周期的结果。当结果不相同时，比较硬件可以包括用于产生异常（例如，引起故障）的异常单元。处理器还包括提交单元，用于在结果相同时提交其中一个结果。

19. 发明申请

US20060248384A1 Method and apparatus for recovery from loss of lock step 有权
公开(公告)号：US20060248384A1
公开(公告)日：2006-11-02
申请号：US11454087
申请日：2006-06-16
申请人： Kevin Safford
发明人： Kevin Safford
IPC分类号： G06F11/00
CPC分类号： G06F11/2038 , G06F11/1641 , G06F11/165 , G06F11/1658 , G06F11/2025 , G06F2201/845
摘要： An apparatus, operating on an advanced multi-core processor architecture, and a corresponding method, are used to enhance recovery from loss of lock step in a multi-processor computer system. The apparatus for recovery from loss of lock step includes multiple processor units operating in the computer system, each of the processor units having at least two processor units operating in lock step, and at least one idle processor unit operating in lock step; and a controller coupled to the two processor units operating in lock step and the idle processor unit. The controller includes mechanisms for copying an architected state of each of the two lock step processor units to the idle processor unit.

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