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11. 发明申请

US20110117715A1 Methods of Forming Capacitors For Semiconductor Memory Devices 有权
标题翻译：半导体存储器件形成电容器的方法
公开(公告)号：US20110117715A1
公开(公告)日：2011-05-19
申请号：US13010297
申请日：2011-01-20
申请人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
发明人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
摘要翻译：公开了一种半导体存储器件的电容器及其形成方法。衬垫层间绝缘层设置在有源区的半导体衬底上。着陆垫和中央着陆垫分别设置在活动区域的周边部分和中心部分中，以穿透垫层间绝缘层。中央着陆垫的上表面与着陆垫的上表面具有不同的面积。掩埋层间绝缘层形成在焊盘层间绝缘层上，以覆盖着陆焊盘和中央着陆焊盘。在相应的着陆焊盘上形成埋入的插塞以穿透埋入的层间绝缘层。下电极形成在埋地塞上。

12. 发明授权

US07851354B2 Semiconductor memory device having local etch stopper and method of manufacturing the same 有权
标题翻译：具有局部蚀刻停止器的半导体存储器件及其制造方法
公开(公告)号：US07851354B2
公开(公告)日：2010-12-14
申请号：US12267785
申请日：2008-11-10
申请人： Jung-woo Seo , Jong-seo Hong , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Young-sun Cho
发明人： Jung-woo Seo , Jong-seo Hong , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Young-sun Cho
IPC分类号： H01L21/4763
CPC分类号： H01L21/76895 , H01L21/76837 , H01L21/76885 , H01L21/76897 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
摘要翻译：半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

13. 发明授权

US07074725B2 Method for forming a storage node of a capacitor 失效
标题翻译：用于形成电容器的存储节点的方法
公开(公告)号：US07074725B2
公开(公告)日：2006-07-11
申请号：US10641636
申请日：2003-08-14
申请人： Jun-Sik Hong , Young-Ki Hong , Tae-Hyuk Ahn , Jong-Seo Hong
发明人： Jun-Sik Hong , Young-Ki Hong , Tae-Hyuk Ahn , Jong-Seo Hong
IPC分类号： H01L21/302
CPC分类号： H01L27/10852 , H01L21/76802 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L28/91
摘要： An improved method of manufacturing a capacitor on a semiconductor substrate is disclosed. A portion of an insulation film on a semiconductor substrate is etched to form a first opening in the insulation film. A passivation film is formed on the insulation film and within the first opening thereof. A portion of the passivation film on a bottom of the first opening is thinner than portions of the passivation film on the insulation film and on a sidewall of the first opening. The passivation film is etched to expose the bottom of the first opening.
摘要翻译：公开了一种在半导体衬底上制造电容器的改进方法。半导体衬底上的绝缘膜的一部分被蚀刻以在绝缘膜中形成第一开口。在绝缘膜上及其第一开口内形成钝化膜。第一开口的底部上的钝化膜的一部分比绝缘膜上的钝化膜和第一开口的侧壁上的钝化膜的部分薄。钝化膜被蚀刻以露出第一开口的底部。

14. 发明申请

US20060138561A1 Semiconductor device having raised cell landing pad and method of fabricating the same 失效
公开(公告)号：US20060138561A1
公开(公告)日：2006-06-29
申请号：US11268551
申请日：2005-11-08
申请人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
发明人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
IPC分类号： H01L29/76 , H01L21/44
CPC分类号： H01L27/10855 , H01L21/76895
摘要： A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.

15. 发明授权

US5252177A Method for forming a multilayer wiring of a semiconductor device 失效
标题翻译：用于形成半导体器件的多层布线的方法
公开(公告)号：US5252177A
公开(公告)日：1993-10-12
申请号：US736772
申请日：1991-07-29
申请人： Jong-Seo Hong , Jin-Hong Kim , Jung-In Hong
发明人： Jong-Seo Hong , Jin-Hong Kim , Jung-In Hong
IPC分类号： H01L21/30 , H01L21/027 , H01L21/304 , H01L21/3205 , H01L21/768 , H01L23/52 , B44C1/22 , C23F7/00
CPC分类号： H01L21/76838 , H01L21/76802 , H01L21/76877
摘要： A method for forming a multilayer wiring, in a method for manufacturing a semiconductor device, is disclosed. The method comprises: forming a contact hole 33 on the surface of a conductive layer 29 by a photolithography, removing a photoresist by using plasma ashing at a predetermined temperature, pressure and amount of oxygen per unit cubic, and simultaneously forming a protective layer 35 consisting of a oxide layer on the surface of the exposed conductive layer. Thus, damage of the surface of wiring caused by the chemical reaction of an organic solvent and water in the subsequent process thereof, is prevented, to provide high density and high speed semiconductor integrated circuit whose electrode characteristics between two wiring layers is improved.
摘要翻译：公开了一种用于形成多层布线的方法，在半导体器件的制造方法中。该方法包括：通过光刻在导电层29的表面上形成接触孔33，通过在预定温度下使用等离子体灰化，压力和每单位立方体的氧量来除去光致抗蚀剂，同时形成保护层35，其包括的暴露的导电层的表面上的氧化物层。因此，防止了在其后续过程中由有机溶剂和水的化学反应引起的布线表面的损伤，从而提供了其两个布线层之间的电极特性提高的高密度和高速的半导体集成电路。

16. 发明授权

US08569140B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08569140B2
公开(公告)日：2013-10-29
申请号：US13194030
申请日：2011-07-29
申请人： Kyu-Tae Kim , Jong-Seo Hong , Tae-Han Kim
发明人： Kyu-Tae Kim , Jong-Seo Hong , Tae-Han Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/28238 , H01L29/42376 , H01L29/4966 , H01L29/66553 , H01L29/66628 , H01L29/7834
摘要： A method for fabricating a semiconductor device is disclosed. One embodiment of the method includes forming a dummy gate pattern on a substrate, forming an interlayer dielectric film that covers the dummy gate pattern, exposing a top surface of the dummy gate pattern, selectively removing the dummy gate pattern to form a first gate trench, forming a sacrificial layer pattern over a top surface of the substrate in the first gate trench, the sacrificial layer pattern leaving a top portion of the first gate trench exposed, increasing an upper width of the exposed top portion of the first gate trench to form a second gate trench, and removing the sacrificial layer pattern in the second gate trench, and forming a non-dummy gate pattern in the second gate trench.
摘要翻译：公开了一种制造半导体器件的方法。该方法的一个实施例包括在衬底上形成伪栅极图案，形成覆盖伪栅极图案的层间电介质膜，暴露伪栅极图案的顶表面，选择性地去除伪栅极图案以形成第一栅极沟槽，在所述第一栅极沟槽中的所述衬底的顶表面上形成牺牲层图案，所述牺牲层图案离开所述第一栅极沟槽的顶部部分而暴露，从而增加所述第一栅极沟槽的暴露顶部的上部宽度，以形成第二栅极沟槽，并且去除第二栅极沟槽中的牺牲层图案，以及在第二栅极沟槽中形成非虚拟栅极图案。

17. 发明授权

US07888724B2 Capacitors for semiconductor memory devices 有权
标题翻译：半导体存储器件的电容器
公开(公告)号：US07888724B2
公开(公告)日：2011-02-15
申请号：US11316166
申请日：2005-12-22
申请人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
发明人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
摘要翻译：公开了一种半导体存储器件的电容器及其形成方法。衬垫层间绝缘层设置在有源区的半导体衬底上。着陆垫和中央着陆垫分别设置在活动区域的周边部分和中心部分中，以穿透垫层间绝缘层。中央着陆垫的上表面与着陆垫的上表面具有不同的面积。掩埋层间绝缘层形成在焊盘层间绝缘层上，以覆盖着陆焊盘和中央着陆焊盘。在相应的着陆焊盘上形成埋入的插塞以穿透埋入的层间绝缘层。下电极形成在埋地塞上。

18. 发明授权

US07511328B2 Semiconductor device having raised cell landing pad and method of fabricating the same 失效
标题翻译：具有升高电池着陆垫的半导体器件及其制造方法
公开(公告)号：US07511328B2
公开(公告)日：2009-03-31
申请号：US11268551
申请日：2005-11-08
申请人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
发明人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
IPC分类号： H01L27/108
CPC分类号： H01L27/10855 , H01L21/76895
摘要： A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.
摘要翻译：半导体器件及其制造方法具有焊盘延伸部分，该半导体器件包括限定有源区的隔离层和穿过有源区的栅电极。源极区域设置在栅电极的一侧的有源区中，并且在栅电极的第二侧的有源区中设置有漏极区。第一层间绝缘层覆盖半导体衬底。源着陆焊盘电连接到源极区域，并且漏极接地焊盘电连接到漏极区域。垫片延伸部分层压在源着陆垫和排水着陆垫的一个或多个上。焊盘延伸部分具有位于与源着陆焊盘和排水接地焊盘的上表面对应的平面上方的平面中的上表面。

19. 发明申请

US20060186479A1 Semiconductor memory device having local etch stopper and method of manufacturing the same 有权
标题翻译：具有局部蚀刻停止器的半导体存储器件及其制造方法
公开(公告)号：US20060186479A1
公开(公告)日：2006-08-24
申请号：US11354175
申请日：2006-02-15
申请人： Jung-woo Seo , Jong-seo Hong , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Young-sun Cho
发明人： Jung-woo Seo , Jong-seo Hong , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Young-sun Cho
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76895 , H01L21/76837 , H01L21/76885 , H01L21/76897 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
摘要翻译：半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

20. 发明申请

US20060222966A1 Mask layout and method of forming contact pad using the same 失效
标题翻译：使用其形成接触垫的掩模布局和方法
公开(公告)号：US20060222966A1
公开(公告)日：2006-10-05
申请号：US11342560
申请日：2006-01-31
申请人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
发明人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： H01L21/31144 , G03F1/00 , H01L21/76897
摘要： Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.
摘要翻译：提供了使用这种光掩模的接触光掩模和方法来制造半导体器件，并在暴露在栅极线之间的有源区域的部分上形成接触插塞。细长的有源区域被排列成一系列平行的组，每个组又沿它们的纵向轴线对准，以与栅极线形成锐角。接触光掩模包括以平行线布置的多个开口，其以与先前形成的栅极线偏移的角度排列，并且可以平行于有源区域，或者可以与两个活动组的轴线偏移的角度对准区域和栅极线。使用这种光掩模形成接触塞的方法可以提供增加的加工余量，并且扩展了展示增加的集成密度和/或构建到更苛刻的设计规则的半导体器件的常规曝光设备的效用。

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