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11. 发明授权

US08252681B2 Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls 有权
标题翻译：形成其中具有部分氮化侧壁的导电层的集成电路器件的方法
公开(公告)号：US08252681B2
公开(公告)日：2012-08-28
申请号：US12536865
申请日：2009-08-06
申请人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
IPC分类号： H01L21/44
CPC分类号： H01L21/28061 , H01L21/28247 , H01L21/3211 , H01L21/32137 , H01L21/32139 , H01L27/10873 , H01L27/11 , H01L27/1104
摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
摘要翻译：形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

12. 发明申请

US20140322832A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140322832A1
公开(公告)日：2014-10-30
申请号：US14100651
申请日：2013-12-09
申请人： Tae-Gon KIM , Jong-Hoon KANG , Jae-Young AHN , Jun-Kyu YANG , Han-Mei CHOI , Ki-Hyun HWANG
发明人： Tae-Gon KIM , Jong-Hoon KANG , Jae-Young AHN , Jun-Kyu YANG , Han-Mei CHOI , Ki-Hyun HWANG
IPC分类号： H01L21/66 , H01L21/3065
CPC分类号： H01L22/12 , H01L21/31116 , H01L22/20 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.
摘要翻译：根据本发明构思的示例性实施例，制造半导体器件的方法包括：形成初步叠层结构，所述预备叠层结构限定通孔; 在通孔中形成保护层和电介质层; 在通孔中形成通道图案，间隙填充图案和接触图案; 在预备堆叠结构上形成偏移氧化物; 测量偏移氧化物的厚度数据; 并使用反应性气体簇离子束扫描偏移氧化物。扫描偏移氧化物包括基于测量的偏移氧化物的厚度数据设置扫描速度，并形成气体簇。

13. 发明授权

US08691649B2 Methods of forming recessed channel array transistors and methods of manufacturing semiconductor devices 有权
标题翻译：形成凹槽阵列晶体管的方法和制造半导体器件的方法
公开(公告)号：US08691649B2
公开(公告)日：2014-04-08
申请号：US13151494
申请日：2011-06-02
申请人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.
摘要翻译：在制造凹陷通道阵列晶体管的方法中，可以在衬底的有源区中形成凹部。可以在衬底上进行等离子体氧化处理，以在凹槽的内表面和衬底的上表面上形成预备栅氧化层。可以在预选择栅极氧化物层的表面吸收水分以形成栅极氧化物层。可以在栅极氧化物层上形成栅电极以填充凹部。源极/漏极区域可以形成在栅电极的两侧的衬底的上表面中。因此，氧化物层可以具有均匀的厚度分布和致密结构。

14. 发明申请

US20090325356A1 METHODS OF FORMING A LOW TEMPERATURE DEPOSITION LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：形成低温沉积层的方法和使用其制造半导体器件的方法
公开(公告)号：US20090325356A1
公开(公告)日：2009-12-31
申请号：US12432500
申请日：2009-04-29
申请人： Dong-Woon SHIN , Si-Young Choi , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Dong-Woon SHIN , Si-Young Choi , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L21/336 , H01L21/31 , H01L21/426
CPC分类号： H01L21/02274 , H01L21/0217 , H01L21/02211 , H01L21/2236 , H01L21/2652 , H01L21/26546 , H01L21/2658 , H01L21/3185 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/6659
摘要： Provided are methods of forming a low temperature deposition layer and methods of manufacturing a semiconductor device using the same. The method of manufacturing a semiconductor device comprises forming a mask layer exposing a gate pattern on a substrate on which the gate pattern is formed, forming a sacrifice layer on the mask layer and on a substrate not covered by the mask layer using a plasma ion immersion implantation and deposition (PIIID), and doping a substrate adjacent to both sidewalls of the gate pattern with an impurity.
摘要翻译：提供形成低温沉积层的方法和使用其制造半导体器件的方法。制造半导体器件的方法包括：在掩模层上形成掩模层，在其上形成栅极图案的衬底上露出栅极图案，在掩模层上形成牺牲层，并在未被掩模层覆盖的衬底上使用等离子体离子浸没注入和沉积（PIIID），并且用杂质掺杂与栅极图案的两个侧壁相邻的衬底。

15. 发明申请

US20090315069A1 THIN GALLIUM NITRIDE LIGHT EMITTING DIODE DEVICE 审中-公开
标题翻译：薄硝酸钠发光二极管器件
公开(公告)号：US20090315069A1
公开(公告)日：2009-12-24
申请号：US12550057
申请日：2009-08-28
申请人： Jae Seung LEE , Bu Gon SHIN , Min Ho CHOI , Jong Hoon KANG , Min A YU , Byung Du OH
发明人： Jae Seung LEE , Bu Gon SHIN , Min Ho CHOI , Jong Hoon KANG , Min A YU , Byung Du OH
IPC分类号： H01L33/00
CPC分类号： H01L33/0079 , H01L33/08 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13 , H01L2224/45144 , H01L2224/48091 , H01L2224/49107 , H01L2224/73265 , H01L2924/00014 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Disclosed is a light emitting diode (LED) device that comprises a crystal structure of a sapphire substrate-free gallium nitride (GaN) LED, wherein the crystal structure is mounted on a first surface of a sub-mount substrate in the form of a unit chip, and the first surface of the sub-mount substrate has a surface area greater than the surface area of a region in which the unit chip is bonded. Preforms for manufacturing the LED device and a method for manufacturing the LED device are also disclosed. The sapphire substrate, on which the crystal structure of the light emitting diode has grown, is processed into a unit chip before being removed. Thus, any crack in the crystal structure of the light emitting diode that may occur during the removal of the sapphire substrate can be prevented. Therefore, a thin light emitting diode device can be manufactured in a mass production system.
摘要翻译：公开了一种发光二极管（LED）装置，其包括蓝宝石无基板氮化镓（GaN）LED的晶体结构，其中晶体结构以单元形式安装在子安装基板的第一表面上芯片，并且子安装基板的第一表面具有大于单元芯片接合的区域的表面积的表面积。还公开了用于制造LED器件的预制件和用于制造LED器件的方法。发光二极管的晶体结构在其上生长的蓝宝石衬底在去除之前被处理成单位芯片。因此，可以防止在去除蓝宝石衬底期间可能发生的发光二极管的晶体结构中的任何裂纹。因此，可以在批量生产系统中制造薄型发光二极管装置。

16. 发明申请

US20080176387A1 PLASMA DOPING METHODS USING MULTIPLE SOURCE GASES 审中-公开
标题翻译：使用多种源气体的等离子体掺杂方法
公开(公告)号：US20080176387A1
公开(公告)日：2008-07-24
申请号：US11753791
申请日：2007-05-25
申请人： Jong-hoon Kang , Tai-su Park , Si-young Choi , Min-jin Kim
发明人： Jong-hoon Kang , Tai-su Park , Si-young Choi , Min-jin Kim
IPC分类号： H01L21/265
CPC分类号： H01L21/2236 , H01L21/28035 , H01L21/3215 , H01L21/32155 , H01L29/4916
摘要： A plasma doping method includes providing a substrate including a layer to be doped inside a chamber, and supplying first and second source gases to the layer to achieve a desired doping concentration. The first source gas includes a component configured to increase a thickness of the layer, and the second gas includes a component configured to reduce a thickness of the layer.
摘要翻译：等离子体掺杂方法包括提供包括在室内掺杂的层的衬底，以及将第一和第二源气体供应到层以实现期望的掺杂浓度。第一源气体包括构造成增加层的厚度的部件，并且第二气体包括构造成减小层的厚度的部件。

17. 发明授权

US08800335B2 Method of manufacturing flange for wind towers using ring rolling method 有权
标题翻译：使用环轧法制造风塔法兰的方法
公开(公告)号：US08800335B2
公开(公告)日：2014-08-12
申请号：US13414844
申请日：2012-03-08
申请人： Jong-hoon Kang , Hyun-jun Kim , Hong-il Jo , Young-myung Kim
发明人： Jong-hoon Kang , Hyun-jun Kim , Hong-il Jo , Young-myung Kim
IPC分类号： B21D22/00 , B21D22/16
CPC分类号： B21H1/06
摘要： Disclosed herein is a method of manufacturing a flange for wind towers through a ring rolling process. The ring rolling process makes use of a ring rolling machine. The ring rolling machine includes a main roll which presses a circumferential outer surface of a blank, a pressure roll which presses a circumferential inner surface of the blank, and a pair of axial rolls which press upper and lower surfaces of the blank. The method includes expanding an inner diameter and outer diameter of the blank using the ring rolling machine, transferring the pressure roll vertically so that a protrusion provided on a circumferential outer surface of the pressure roll comes into contact with the circumferential inner surface of the blank, and forming a depression in the circumferential inner surface of the blank using the protrusion of the pressure roll.
摘要翻译：本文公开了一种通过环轧工艺制造风塔的凸缘的方法。环轧过程利用环轧机。环轧机包括挤压坯料的周向外表面的主辊，挤压坯料的周向内表面的压辊以及挤压坯件的上表面和下表面的一对轴向辊。该方法包括使用环轧机使坯料的内径和外径扩大，垂直地传送压力辊，使得设置在压力辊的周向外表面上的突起与坯料的周向内表面接触，并且使用压力辊的突起在坯料的周向内表面中形成凹陷。

18. 发明申请

US20130205857A1 METHOD OF MANUFACTURING FLANGE FOR WIND TOWERS USING RING ROLLING METHOD 有权
标题翻译：使用环形滚动方法制造风力发电机的法兰的方法
公开(公告)号：US20130205857A1
公开(公告)日：2013-08-15
申请号：US13414844
申请日：2012-03-08
申请人： Jong-hoon KANG , Hyun-jun Kim , Hong-il Jo , Young-myung Kim
发明人： Jong-hoon KANG , Hyun-jun Kim , Hong-il Jo , Young-myung Kim
IPC分类号： B21H1/06 , B21D31/04
CPC分类号： B21H1/06
摘要： Disclosed herein is a method of manufacturing a flange for wind towers through a ring rolling process. The ring rolling process makes use of a ring rolling machine. The ring rolling machine includes a main roll which presses a circumferential outer surface of a blank, a pressure roll which presses a circumferential inner surface of the blank, and a pair of axial rolls which press upper and lower surfaces of the blank. The method includes expanding an inner diameter and outer diameter of the blank using the ring rolling machine, transferring the pressure roll vertically so that a protrusion provided on a circumferential outer surface of the pressure roll comes into contact with the circumferential inner surface of the blank, and forming a depression in the circumferential inner surface of the blank using the protrusion of the pressure roll.
摘要翻译：本文公开了一种通过环轧工艺制造风塔的凸缘的方法。环轧过程利用环轧机。环轧机包括挤压坯料的周向外表面的主辊，挤压坯料的周向内表面的压辊以及挤压坯件的上表面和下表面的一对轴向辊。该方法包括使用环轧机使坯料的内径和外径扩大，垂直地传送压力辊，使得设置在压力辊的周向外表面上的突起与坯料的周向内表面接触，并且使用压力辊的突起在坯料的周向内表面中形成凹陷。

19. 发明授权

US08501611B2 Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls 有权
标题翻译：形成其中具有部分氮化侧壁的导电层的集成电路器件的方法
公开(公告)号：US08501611B2
公开(公告)日：2013-08-06
申请号：US13551251
申请日：2012-07-17
申请人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
IPC分类号： H01L21/3205
CPC分类号： H01L21/28061 , H01L21/28247 , H01L21/3211 , H01L21/32137 , H01L21/32139 , H01L27/10873 , H01L27/11 , H01L27/1104
摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
摘要翻译：形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

20. 发明申请

US20130115760A1 METHOD OF FORMING A THIN LAYER STRUCTURE 有权
标题翻译：形成薄层结构的方法
公开(公告)号：US20130115760A1
公开(公告)日：2013-05-09
申请号：US13596339
申请日：2012-08-28
申请人： JONG-HOON KANG , BONG-JIN KUH , TAE-GON KIM , HAN-MEI CHOI , KI-CHUL KIM , EUN-YOUNG JO
发明人： JONG-HOON KANG , BONG-JIN KUH , TAE-GON KIM , HAN-MEI CHOI , KI-CHUL KIM , EUN-YOUNG JO
IPC分类号： H01L21/20
CPC分类号： H01L21/02433 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/268 , H01L21/324 , H01L29/045
摘要： A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets.
摘要翻译：薄层结构包括衬底，暴露衬底的上表面的一部分的阻挡图案以及在衬底的上表面部分上的单晶半导体层，其中所述衬底的所有外表面单晶半导体层具有<100>晶体取向。薄层结构由SEG工艺形成，其中控制温度以防止原子沿着朝向衬底上表面的中心部分的方向迁移。因此，该层的侧壁表面将不由小平面构成。

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