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11. 发明授权

US07042914B2 Calibrated data communication system and method 失效
公开(公告)号：US07042914B2
公开(公告)日：2006-05-09
申请号：US10684618
申请日：2003-10-13
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

12. 发明授权

US06949958B2 Phase comparator capable of tolerating a non-50% duty-cycle clocks 失效
标题翻译：相位比较器能够容忍非50％的占空比时钟
公开(公告)号：US06949958B2
公开(公告)日：2005-09-27
申请号：US10282531
申请日：2002-10-28
申请人： Jared LeVan Zerbe , Michael Tak-kei Ching , Abhijit M. Abhyankar , Richard M. Barth , Andy Peng-Pui Chan , Paul G. Davis , William F. Stonecypher
发明人： Jared LeVan Zerbe , Michael Tak-kei Ching , Abhijit M. Abhyankar , Richard M. Barth , Andy Peng-Pui Chan , Paul G. Davis , William F. Stonecypher
IPC分类号： G06F1/10 , G06F13/42 , H04L7/00 , H04L7/02 , H04L7/033 , H04L7/04 , G01R25/00
CPC分类号： G06F1/12 , G06F13/423 , H03L7/085 , H04L7/0012 , H04L7/0045 , H04L7/0054 , H04L7/02 , H04L7/0337
摘要： A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.
摘要翻译：公开了一种在两个同步（相同频率，不同相位）时钟域之间实现最小延迟数据传输的方法和电路。该电路支持两个时钟域之间的任意相位关系，并且在保持相同的输出数据延迟之后容忍初始化之后的温度和电压偏移。在一个实施例中，该电路用于总线系统以将数据从接收域，时钟重新传输到发射域时钟。在这种系统中，这两个时钟之间的相位关系由设备总线位置设置，因此不是精确的。通过支持任意相位重新同步，本公开允许理论上无限长的总线长度，从而不限制器件数量，以及沿着总线的器件的任意放置。这最终允许为很长的总线支持多个延迟域。

13. 发明授权

US06643787B1 Bus system optimization 有权
标题翻译：总线系统优化
公开(公告)号：US06643787B1
公开(公告)日：2003-11-04
申请号：US09421073
申请日：1999-10-19
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： G06F1340
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A bus system comprising a master connected to one or more slave devices via a bus is disclosed. The bus system is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device. The offsets are used to optimize transfer timing (including duty cycle characteristics), signal equalization, and voltage levels for data exchanged between the master and the slave devices.
摘要翻译：公开了一种总线系统，包括经由总线连接到一个或多个从设备的主设备。总线系统能够在校准阶段期间有效地传达控制信息，并且单独地确定每个从设备的适当的定时和/或电压偏移。偏移量用于优化主设备和从设备之间交换的数据的传输定时（包括占空比特性），信号均衡和电压电平。

14. 发明授权

US08331512B2 Phase control block for managing multiple clock domains in systems with frequency offsets 有权
标题翻译：用于在具有频率偏移的系统中管理多个时钟域的相位控制块
公开(公告)号：US08331512B2
公开(公告)日：2012-12-11
申请号：US12225999
申请日：2007-04-04
申请人： Hae-Chang Lee , Jared LeVan Zerbe , Carl William Werner
发明人： Hae-Chang Lee , Jared LeVan Zerbe , Carl William Werner
IPC分类号： H04L7/00
CPC分类号： H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
摘要： A circuit for performing clock recovery according to a received digital signal (30). The circuit includes at least an edge sampler (105) and a data sampler (145) for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock (25) and data clock (20) signals offset in phase from one another to the respective clock inputs of the edge sampler (105) and the data sampler (145). The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.
摘要翻译：一种用于根据接收到的数字信号（30）执行时钟恢复的电路。该电路至少包括用于采样数字信号的边缘采样器（105）和数据采样器（145），以及时钟信号提供电路。时钟信号供应电路提供边缘时钟（25）和数据时钟（20）信号，其相位偏移到边缘采样器（105）和数据采样器（145）的相应时钟输入。时钟信号供给电路可操作以选择性地改变边缘和数据时钟信号之间的相位偏移。

15. 发明授权

US07535933B2 Calibrated data communication system and method 有权
标题翻译：校准数据通信系统及方法
公开(公告)号：US07535933B2
公开(公告)日：2009-05-19
申请号：US11327213
申请日：2006-01-05
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.
摘要翻译：一种系统包括第一集成电路装置和第二集成电路装置。第一设备将数据序列发送到第二集成电路设备，并且第二设备对数据序列进行采样以产生接收机数据。然后，第二设备将接收机数据发送回第一设备。在第一集成电路装置内，执行数据序列与接收机数据之间的比较，并且基于比较，第一装置产生表示经校准的定时偏移的信息。第一设备使用代表校准的定时偏移的信息来调整与从第一集成电路向第二集成电路传送写入数据相关联的定时。

16. 发明授权

US07288973B2 Method and apparatus for fail-safe resynchronization with minimum latency 有权
标题翻译：具有最小延迟的故障安全重新同步的方法和装置
公开(公告)号：US07288973B2
公开(公告)日：2007-10-30
申请号：US11237276
申请日：2005-09-27
申请人： Jared LeVan Zerbe , Michael Tak-kei Ching , Abhijit M. Abhyankar , Richard M. Barth , Andy Peng-Pui Chan , Paul G. Davis , William F. Stonecypher
发明人： Jared LeVan Zerbe , Michael Tak-kei Ching , Abhijit M. Abhyankar , Richard M. Barth , Andy Peng-Pui Chan , Paul G. Davis , William F. Stonecypher
IPC分类号： H03L7/00
CPC分类号： G06F1/12 , G06F13/423 , H03L7/085 , H04L7/0012 , H04L7/0045 , H04L7/0054 , H04L7/02 , H04L7/0337
摘要： A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.
摘要翻译：公开了一种在两个同步（相同频率，不同相位）时钟域之间实现最小延迟数据传输的方法和电路。该电路支持两个时钟域之间的任意相位关系，并且在保持相同的输出数据延迟之后容忍初始化之后的温度和电压偏移。在一个实施例中，该电路用于总线系统以将数据从接收域，时钟重新传输到发射域时钟。在这种系统中，这两个时钟之间的相位关系由设备总线位置设置，因此不是精确的。通过支持任意相位重新同步，本公开允许理论上无限长的总线长度，从而不限制器件数量，以及沿着总线的器件的任意放置。这最终允许为很长的总线支持多个延迟域。

17. 发明授权

US07133463B1 Linear transformation circuits 失效
标题翻译：线性变换电路
公开(公告)号：US07133463B1
公开(公告)日：2006-11-07
申请号：US11213352
申请日：2005-08-25
申请人： Amir Amirkhany , Vladimir Stojanovic , Elad Alon , Jared LeVan Zerbe , Mark A. Horowitz
发明人： Amir Amirkhany , Vladimir Stojanovic , Elad Alon , Jared LeVan Zerbe , Mark A. Horowitz
IPC分类号： H04L27/04
CPC分类号： G06F17/141 , G06J1/005
摘要： A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of weighted sums of the N digital data symbols. Each respective weighted sum is defined by a respective set of pre-determined weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective weighted sum of the N analog data symbols. Each respective weighted sum is defined by a respective set of pre-determined weighting values in a second matrix.
摘要翻译：变换电路包括第一电路和第二电路。第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。第一电路通过产生N个数字数据符号的加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。每个相应的加权和由第一矩阵中的预定加权值的相应集合定义。第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的各自的加权和。每个相应的加权和由第二矩阵中的预定加权值的相应集合来定义。

18. 发明授权

US08610307B2 Optimized power supply for an electronic system 有权
公开(公告)号：US08610307B2
公开(公告)日：2013-12-17
申请号：US13747417
申请日：2013-01-22
申请人： Jared LeVan Zerbe , Jaeha Kim , Yohan U. Frans , Huy M. Nguyen
发明人： Jared LeVan Zerbe , Jaeha Kim , Yohan U. Frans , Huy M. Nguyen
IPC分类号： H02J1/10
CPC分类号： G05F1/10 , G06F1/26 , Y10T307/406 , Y10T307/50
摘要： A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.

19. 发明申请

US20120204054A1 Memory System with Calibrated Data Communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US20120204054A1
公开(公告)日：2012-08-09
申请号：US13447080
申请日：2012-04-13
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
摘要翻译：集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

20. 发明申请

US20100019834A1 Optimized Power Supply for an Electronic System 有权
标题翻译：电子系统优化电源
公开(公告)号：US20100019834A1
公开(公告)日：2010-01-28
申请号：US12528566
申请日：2008-02-28
申请人： Jared Levan Zerbe , Jaeha Kim , Yohan U. Frans , Huy M. Nguyen
发明人： Jared Levan Zerbe , Jaeha Kim , Yohan U. Frans , Huy M. Nguyen
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , G06F1/26 , Y10T307/406 , Y10T307/50
摘要： A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.
摘要翻译：根据与有线通信链路相关联的性能度量来调整与有线通信链路耦合的电子设备的电压供应的方法。基于性能度量产生电压调整信号。然后，电压调整信号用于更新对电子设备的电压供应。

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