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11. 发明申请

US20100141985A1 Print Job Separation 有权
标题翻译：打印作业分离
公开(公告)号：US20100141985A1
公开(公告)日：2010-06-10
申请号：US12515128
申请日：2007-11-07
申请人： Amir Noy , Ilan Shimony
发明人： Amir Noy , Ilan Shimony
IPC分类号： G06F3/12
CPC分类号： G06F3/1254 , G06F3/1204 , G06F3/1285
摘要： A method for separating multiple print jobs sent by one or more computers to a document printer, the method including printing a first banner at the edge of a top sheet of a first print job, and printing a second banner at the edge of a top sheet of a second print job.
摘要翻译：一种用于将由一个或多个计算机发送的多个打印作业分离到文档打印机的方法，所述方法包括在第一打印作业的顶片的边缘处打印第一横幅，以及在顶页的边缘打印第二横幅的第二个打印作业。

12. 发明申请

US20090178135A1 LANGUAGE INDEPENDENT LOGIN METHOD AND SYSTEM 失效
标题翻译：语言独立登录方法和系统
公开(公告)号：US20090178135A1
公开(公告)日：2009-07-09
申请号：US12126905
申请日：2008-05-25
申请人： Oded Dubovsky , Itzhack Goldberg , Ido Levy , Ilan Shimony , Grant D. Williamson
发明人： Oded Dubovsky , Itzhack Goldberg , Ido Levy , Ilan Shimony , Grant D. Williamson
IPC分类号： H04L9/32 , G06F21/00 , G05B19/00
CPC分类号： G06F21/36
摘要： The present invention prevents illegitimate access to a user computing machine. A method in accordance with an embodiment includes: setting an authentication routine in the user computing machine; generating a virtual keyboard on the user computing machine; entering a user identification through the virtual keyboard, the user identification being entered according to a virtual keyboard form factor; comparing the entered user identification with a secure user identification previously stored in the user computing machine; and validating the user access to the user computing machine if a match occurs, otherwise denying access.
摘要翻译：本发明防止非法访问用户计算机。根据实施例的方法包括：在用户计算机中设置认证例程; 在所述用户计算机上生成虚拟键盘; 通过虚拟键盘输入用户识别，根据虚拟键盘的形状来输入用户标识; 将输入的用户标识与先前存储在用户计算机中的安全用户标识进行比较; 并且如果发生匹配则验证用户对用户计算机的访问，否则拒绝访问。

13. 发明申请

US20090031142A1 System, Method and Computer Program Product for Processing a Memory Page 审中-公开
标题翻译：用于处理内存页的系统，方法和计算机程序产品
公开(公告)号：US20090031142A1
公开(公告)日：2009-01-29
申请号：US11782646
申请日：2007-07-25
申请人： Shai Halevi , William Eric Hall , Hugo Mario Krawczyk , Julian Satran , Ilan Shimony
发明人： Shai Halevi , William Eric Hall , Hugo Mario Krawczyk , Julian Satran , Ilan Shimony
IPC分类号： H04L9/00
CPC分类号： G06F12/1408 , G06F12/1009
摘要： A method for processing a memory page, the method includes: retrieving, in response to a request to provide a first memory page to a processor, first memory page metadata associated with first memory page address information; wherein the first memory page address information is stored in a memory page table; and performing a page operation in response to the memory page metadata; wherein the page operation is selected from a group consisting of compression, cryptography, searching a page for a virus signature, searching a page for digital right management signature, error correction code verification, error correction code addition.
摘要翻译：一种用于处理存储器页面的方法，所述方法包括：响应于向处理器提供第一存储器页面的请求，检索与第一存储器页面地址信息相关联的第一存储器页面元数据; 其中所述第一存储器页地址信息被存储在存储器页表中; 以及响应于所述存储器页面元数据执行页面操作; 其中所述页面操作是从包括压缩，加密，搜索病毒签名的页面，搜索数字版权管理签名的页面，纠错码验证，纠错码添加组成的组中选择的。

14. 发明申请

US20080189392A1 COMPUTER SYSTEM WITH LAN-BASED I/O 审中-公开
标题翻译：具有基于LAN的I / O的计算机系统
公开(公告)号：US20080189392A1
公开(公告)日：2008-08-07
申请号：US12062211
申请日：2008-04-03
申请人： Alain Azagury , Michael Rodeh , Julian Satran , Ilan Shimony , T. Basil Smith , Dhruv M. Desai
发明人： Alain Azagury , Michael Rodeh , Julian Satran , Ilan Shimony , T. Basil Smith , Dhruv M. Desai
IPC分类号： G06F15/16
CPC分类号： H04L67/08 , H04L2212/00
摘要： A computer system includes a local area network (LAN) and a plurality of computers. Each of the computers includes at least one central processing unit (CPU) and a LAN interface, which is coupled to communicate over the LAN, while the computers include no on-board input/output (I/O) device controllers other than the LAN interface. One or more peripheral devices are coupled to communicate with the computers over the LAN.
摘要翻译：计算机系统包括局域网（LAN）和多个计算机。每个计算机包括至少一个中央处理单元（CPU）和LAN接口，其被耦合以通过LAN进行通信，而计算机不包括除LAN之外的板上输入/输出（I / O）设备控制器接口。一个或多个外围设备被耦合以通过LAN与计算机通信。

15. 发明申请

US20080028357A1 METHOD OF AUTOMATIC GENERATION OF MICRO CLOCK GATING FOR REDUCING POWER CONSUMPTION 审中-公开
标题翻译：用于降低功耗的微型时钟自动生成方法
公开(公告)号：US20080028357A1
公开(公告)日：2008-01-31
申请号：US11830069
申请日：2007-07-30
申请人： Ilan Shimony
发明人： Ilan Shimony
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62 , G06F2217/78
摘要： A method and apparatus for reducing transitions thereby reducing power consumption for a clocked output state-holding element having inputs that are respective logic functions of one or more clocked input state-holding elements. A respective valid line is associated with each of the clocked input state-holding elements whose value indicates whether a respective input of the clocked input state-holding element is valid. The clocked output state-holding element is clock gated only if the respective inputs of all of the clocked input state-holding elements coupled to the clocked output state-holding element are indicated as being valid.
摘要翻译：一种用于减少转换的方法和装置，从而降低具有作为一个或多个时钟输入状态保持元件的相应逻辑功能的输入的时钟输出状态保持元件的功耗。相应的有效行与每个时钟输入状态保持元件相关联，其值表示时钟输入状态保持元件的相应输入是否有效。时钟输出状态保持元件仅在耦合到时钟输出状态保持元件的所有时钟输入状态保持元件的相应输入被指示为有效时才被选通时钟门控。

16. 发明申请

US20060262799A1 Transmit flow for network acceleration architecture 有权
标题翻译：传输流网络加速架构
公开(公告)号：US20060262799A1
公开(公告)日：2006-11-23
申请号：US11132853
申请日：2005-05-19
申请人： Giora Biran , Zorik Machulsky , Vadim Makhervaks , Renato Recio , Julian Satran , Leah Shalev , Ilan Shimony
发明人： Giora Biran , Zorik Machulsky , Vadim Makhervaks , Renato Recio , Julian Satran , Leah Shalev , Ilan Shimony
IPC分类号： H04L12/56
CPC分类号： H04L69/16 , H04L69/12 , H04L69/161 , H04L69/163
摘要： A method for receiving data in a network acceleration architecture for use with TCP (transport control protocol), iSCSI (Internet Small Computer System Interface) and/or RDMA (Remote Direct Memory Access) over TCP, including providing a hardware acceleration engine, called a streamer, adapted for communication with and processing data from a consumer application in a system that supports TCP, iSCSI and RDMA over TCP, providing a software protocol processor adapted for carrying out TCP implementation, the software control processor being called a TCE (TCP Control Engine), wherein the streamer and the TCE are adapted to operate asynchronously and independently of one another, and transmitting a TCP segment with the streamer.
摘要翻译：一种用于在TCP（传输控制协议），iSCSI（因特网小型计算机系统接口）和/或RDMA（远程直接存储器访问）TCP上使用的网络加速架构中接收数据的方法，包括提供称为流式传输器，适用于通过TCP支持TCP，iSCSI和RDMA的系统中的消费者应用程序的通信和处理数据，提供适用于执行TCP实现的软件协议处理器，该软件控制处理器被称为TCE（TCP控制引擎），其中所述流送器和所述TCE适于彼此异步地且彼此独立地操作，并且与所述流送器传输TCP段。

17. 发明授权

US06735670B1 Forwarding table incorporating hash table and content addressable memory 失效
标题翻译：包含哈希表和内容可寻址内存的转发表
公开(公告)号：US06735670B1
公开(公告)日：2004-05-11
申请号：US09570204
申请日：2000-05-12
申请人： Zvika Bronstein , Opher Yaron , Golan Schzukin , Ilan Shimony
发明人： Zvika Bronstein , Opher Yaron , Golan Schzukin , Ilan Shimony
IPC分类号： G06F1200
CPC分类号： H04L45/7453 , H04L45/745 , H04L69/22
摘要： A forwarding table comprising a combination of a hash table and a content addressable memory (CAM). The forwarding table combines a one way hash table and a small CAM to perform the forwarding information retrieval function. The CAM is used when an address cannot be found in the hash table. When MAC addresses are being added to the forwarding table, they are first tried in the hash table. The address is applied to the hash function and a resulting index input to the hash table. If a hit occurs, it indicates that an entry at that index already exists and a location in the CAM is then allocated for that address. As long as the CAM does not become full, a 100% hit rate is guaranteed. During retrieval, the hash table or the CAM forms the forwarding information output to the next processing stage. If an entry is not found in the hash table, it will typically be found in the CAM. If no entry is found in either, the received frame is flooded to all the ports of the network device.
摘要翻译：包括哈希表和内容可寻址存储器（CAM）的组合的转发表。转发表组合单向哈希表和小型CAM来执行转发信息检索功能。当哈希表中找不到地址时，使用CAM。当MAC地址被添加到转发表中时，它们首先在哈希表中尝试。该地址被应用于散列函数，并将生成的索引输入到哈希表。如果发生命中，则表示该索引处的条目已存在，然后为该地址分配CAM中的一个位置。只要CAM没有满了，保证100％的命中率。在检索期间，哈希表或CAM形成输出到下一个处理阶段的转发信息。如果哈希表中没有找到条目，它通常会在CAM中找到。如果没有任何条目被发现，则所接收的帧被洪泛到网络设备的所有端口。

18. 发明授权

US5511219A Mechanism for implementing vector address pointer registers in system having parallel, on-chip DSP module and CPU core 失效
标题翻译：在具有并行，片上DSP模块和CPU内核的系统中实现向量地址指针寄存器的机制
公开(公告)号：US5511219A
公开(公告)日：1996-04-23
申请号：US274589
申请日：1994-07-13
申请人： Ilan Shimony , Zvi Greenfeld
发明人： Ilan Shimony , Zvi Greenfeld
IPC分类号： G06F9/32 , G06F9/38 , G06F11/36 , G06F13/24 , G06F15/78 , H04L27/38 , G06F13/00
CPC分类号： G06F11/3648 , G06F11/3656 , G06F11/3664 , G06F13/24 , G06F15/7842 , G06F9/30167 , G06F9/32 , G06F9/3879 , H04L27/38
摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. The system includes vector address pointer registers together with implementing and wrap-around logic.
摘要翻译：集成数据处理系统包括用于传送指令和数据的共享内部总线。共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线。通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。该系统包括向量地址指针寄存器以及实现和环绕逻辑。

19. 发明授权

US07925801B2 Method and system for protection and security of IO devices using credentials 有权
标题翻译：使用凭证的IO设备的保护和安全的方法和系统
公开(公告)号：US07925801B2
公开(公告)日：2011-04-12
申请号：US11333716
申请日：2006-01-17
申请人： Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III
发明人： Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F21/85 , G06Q20/3821
摘要： A method and system for protection and security of IO devices using credential are provided. The system may include at least one consumer arranged to initiate IO requests from the IO device, and the IO requests may include IO capability allocation and additional parameters. The system may also include an IO resource manager (IORM) arranged to translate the IO capability allocation and additional parameters included in said IO request to a set of capability tokens for the consumer or for a group of consumers, to generate a global key to protect the capability tokens, and further arranged to manage the IO device. The system may further include a channel component arranged to transfer and receive the IO request to and from the IO device.
摘要翻译：提供了使用凭证的IO设备的保护和安全性的方法和系统。该系统可以包括至少一个消费者，被安排为从IO设备发起IO请求，并且IO请求可以包括IO能力分配和附加参数。该系统还可以包括IO资源管理器（IORM），其被配置为将IO能力分配和包括在所述IO请求中的附加参数转换成消费者或一组消费者的一组能力令牌以产生保护的全局密钥能力标记，并进一步安排管理IO设备。该系统还可以包括被配置为向IO设备传送和接收IO请求的信道组件。

20. 发明授权

US07924848B2 Receive flow in a network acceleration architecture 失效
标题翻译：在网络加速架构中接收流量
公开(公告)号：US07924848B2
公开(公告)日：2011-04-12
申请号：US11132101
申请日：2005-05-18
申请人： Giora Biran , Zorik Machulsky , Vadim Makhervaks , Renato John Recio , Julian Satran , Leah Shalev , Ilan Shimony
发明人： Giora Biran , Zorik Machulsky , Vadim Makhervaks , Renato John Recio , Julian Satran , Leah Shalev , Ilan Shimony
IPC分类号： H04L12/28 , G06F15/16 , G06F15/167
CPC分类号： H04L69/16 , H04L69/12 , H04L69/161
摘要： A method for receiving data in a network acceleration architecture for use with TCP (transport control protocol), iSCSI (Internet Small Computer System Interface) and RDMA (Remote Direct Memory Access) over TCP, including providing a hardware acceleration engine, called a streamer, adapted for communication with and processing data from a consumer application in a system that supports TCP, iSCSI and RDMA over TCP, providing a software protocol processor adapted for carrying out TCP implementation, the software control processor being called a TCE (TCP Control Engine), wherein the streamer and the TCE are adapted to operate asynchronously and independently of one another, and receiving an inbound TCP segment with the streamer.
摘要翻译：一种用于在TCP（传输控制协议），iSCSI（因特网小型计算机系统接口）和RDMA（远程直接存储器访问）TCP上使用的网络加速架构中接收数据的方法，包括提供称为流传输器的硬件加速引擎，适用于与支持TCP，iSCSI和RDMA over TCP的系统中的消费者应用程序进行通信和处理数据，提供适于执行TCP实现的软件协议处理器，称为TCE（TCP控制引擎）的软件控制处理器，其中所述流送器和所述TCE适于彼此异步地且独立地操作，并且与所述流送器接收入站TCP段。

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