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11. 发明申请

US20100181639A1 SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100181639A1
公开(公告)日：2010-07-22
申请号：US12356036
申请日：2009-01-19
申请人： Wei-Tsung Huang , Pi-Kuang Chuang , Shih-Ming Chen , Hsiao-Ying Yang
发明人： Wei-Tsung Huang , Pi-Kuang Chuang , Shih-Ming Chen , Hsiao-Ying Yang
IPC分类号： H01L23/58 , H01L21/76
CPC分类号： H01L21/763 , H01L21/823481 , H01L21/823878
摘要： A semiconductor device is provided. The semiconductor device comprises an epitaxial layer disposed on a semiconductor substrate, a plurality of electronic devices disposed on the epitaxial layer and a trench isolation structure disposed between the electric devices. The trench isolation structure comprises a trench in the epitaxial layer and the semiconductor substrate, an oxide liner on the sidewall and bottom of the trench, and a doped polysilicon layer filled in the trench. Moreover, a zero bias voltage can be applied to the doped polysilicon layer. The trench isolation structure can be used for isolating electronic devices having different operation voltages or high-voltage devices.
摘要翻译：提供半导体器件。半导体器件包括设置在半导体衬底上的外延层，设置在外延层上的多个电子器件和设置在电气器件之间的沟槽隔离结构。沟槽隔离结构包括在外延层和半导体衬底中的沟槽，沟槽的侧壁和底部上的氧化物衬垫以及填充在沟槽中的掺杂多晶硅层。此外，零偏压可以施加到掺杂多晶硅层。沟槽隔离结构可以用于隔离具有不同操作电压的电子器件或高压器件。

12. 发明申请

US20090053891A1 Method for fabricating a semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20090053891A1
公开(公告)日：2009-02-26
申请号：US12196384
申请日：2008-08-22
申请人： Yi-Chin Lin , Chia-Wei Hsu , Yeou-Bin Lin , Yi-Tsung Jan , Sung-Min Wei , Chin-Cherng Liao , Pi-Xuang Chuang , Shih-Ming Chen , Hsiao-Ying Yang
发明人： Yi-Chin Lin , Chia-Wei Hsu , Yeou-Bin Lin , Yi-Tsung Jan , Sung-Min Wei , Chin-Cherng Liao , Pi-Xuang Chuang , Shih-Ming Chen , Hsiao-Ying Yang
IPC分类号： H01L21/768
CPC分类号： H01L21/76804 , H01L21/76831 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device for preventing a poisoned via is provided. A substrate with a conductive layer formed thereon is provided. A composite layer is formed over the substrate and the conductive layer, wherein the composite layer comprises a dielectric layer and a spin-on-glass layer. A via hole is formed through the composite layer, wherein the via hole exposes a surface of the conductive layer. A protection layer is formed on a sidewall of the via hole so as to prevent out-gassing from the spin-on-glass layer. A barrier layer is formed on the protection layer and the conductive layer within the via hole. And a metal layer is deposited on the barrier layer within the via hole to fill the via hole.
摘要翻译：提供一种用于制造用于防止中毒的通孔的半导体器件的方法。提供其上形成有导电层的基板。在衬底和导电层上形成复合层，其中复合层包括电介质层和旋涂玻璃层。通过复合层形成通孔，其中通孔露出导电层的表面。在通孔的侧壁上形成保护层，以防止旋涂玻璃层的排气。阻挡层形成在保护层和通孔内的导电层上。并且在通孔内的阻挡层上沉积金属层以填充通孔。

13. 发明授权

US06875658B2 High-voltage device with improved punch through voltage and process for same compatible with low-voltage device process 有权
标题翻译：具有改进的穿通电压和工艺的高压器件，与低电压器件工艺兼容
公开(公告)号：US06875658B2
公开(公告)日：2005-04-05
申请号：US10447152
申请日：2003-05-29
申请人： Hsiao-Ying Yang
发明人： Hsiao-Ying Yang
IPC分类号： H01L21/8234 , H01L27/092 , H01L29/78
CPC分类号： H01L21/823481 , H01L21/823418 , H01L27/0921 , H01L29/7833
摘要： A high-voltage device with improved punch through voltage. A semiconductor silicon substrate has a high-voltage device region on which a gate structure is patterned. A lightly doped region is formed in the substrate and lateral to the gate structure. A spacer is formed on the sidewall of the gate structure. A heavily doped region is formed in the lightly doped region and lateral to the spacer. A lateral distance is kept between the spacer and the heavily doped region.
摘要翻译：具有改善穿孔电压的高压器件。半导体硅衬底具有其上栅极结构被图案化的高电压器件区域。在衬底中形成轻掺杂区域，并在栅极结构的外侧形成。在栅极结构的侧壁上形成间隔物。在轻掺杂区域中形成重掺杂区域并且在间隔物的侧面形成。在间隔物和重掺杂区域之间保持横向距离。

14. 发明授权

US09219012B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09219012B2
公开(公告)日：2015-12-22
申请号：US13294945
申请日：2011-11-11
申请人： Chih-Ping Lin , Pi-Kuang Chuang , Hung-Li Chang , Shih-Ming Chen , Hsiao-Ying Yang
发明人： Chih-Ping Lin , Pi-Kuang Chuang , Hung-Li Chang , Shih-Ming Chen , Hsiao-Ying Yang
IPC分类号： H01L29/00 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823481 , H01L21/823412 , H01L21/823493 , H01L21/823807 , H01L21/823878 , H01L21/823892
摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.
摘要翻译：提供一种制造半导体器件的方法。提供了包括P阱的衬底。在P井中定义了低压装置区域和高压装置区域。在基板上形成光致抗蚀剂层。提供了包括屏蔽区域的光掩模。屏蔽区域对应于高电压设备区域。通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。

15. 发明授权

US08067283B2 Semiconductor device fabricating method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08067283B2
公开(公告)日：2011-11-29
申请号：US12618585
申请日：2009-11-13
申请人： Chih-Ping Lin , Shih-Ming Chen , Hsiao-Ying Yang , Wen-Hsien Liu , Po-Sheng Hu
发明人： Chih-Ping Lin , Shih-Ming Chen , Hsiao-Ying Yang , Wen-Hsien Liu , Po-Sheng Hu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462
摘要： A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of the gate layer, the first gate insulating layer and the second gate insulating layer are removed to form a first gate, a remaining first gate insulating layer, a second gate and a remaining second gate insulating layer. The remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness, wherein a ratio between the first thickness and the second thickness is about 10 to 20. A pair of first spacers and a pair of second spacers are formed on sidewalls of the first gate and the second gate, respectively.
摘要翻译：描述半导体器件制造方法。半导体器件制造方法包括提供基板。分别在基板上形成第一栅极绝缘层和第二栅极绝缘层。门层完全形成。去除栅极层，第一栅极绝缘层和第二栅极绝缘层的一部分以形成第一栅极，剩余的第一栅极绝缘层，第二栅极和剩余的第二栅极绝缘层。未被第一栅极覆盖的剩余的第一栅极绝缘层具有第一厚度，并且未被第二栅极覆盖的剩余的第二栅极绝缘层具有第二厚度，其中第一厚度和第二厚度之间的比率为约10度分别在第一栅极和第二栅极的侧壁上形成一对第一间隔物和一对第二间隔物。

16. 发明授权

US6004853A Method to improve uniformity and the critical dimensions of a DRAM gate structure 有权
标题翻译：提高DRAM门结构的均匀性和关键尺寸的方法
公开(公告)号：US6004853A
公开(公告)日：1999-12-21
申请号：US320753
申请日：1999-05-27
申请人： Hsiao-Ying Yang , Yeh-Sen Lin
发明人： Hsiao-Ying Yang , Yeh-Sen Lin
IPC分类号： H01L21/027 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/0276 , H01L21/28123 , H01L21/31144 , H01L21/32139 , H01L29/6656 , Y10S438/952
摘要： A process for fabricating a straight walled, silicon nitride capped, gate structure, for a MOSFET device, has been developed. The process features the creation of a straight walled, photoresist shape, to be used as an etch mask, during the patterning of the straight walled, silicon nitride capped, gate structure. A silicon oxynitride layer, with a specific thickness range between about 820 to 920 Angstroms, is used as a bottom anti-reflective coating, (BARC), layer, located between an overlying straight walled, photoresist shape, and an underlying silicon nitride capping layer. The BARC layer retards the reflection emitted from a silicon nitride capping layer, during the photolithographic exposure procedure, used for definition of the straight walled, photoresist shape, allowing the desired straight walled, photoresist shape, to be obtained, independent of the thickness of the silicon nitride capping layer. The ability to fabricate straight walled, silicon nitride capped, gate structures, allows control, and uniformity, of channel regions, located underlying the straight walled, silicon nitride capped, gate structure, and between source/drain regions, self-aligned to the straight walled, silicon nitride capped, gate structures, to be realized.
摘要翻译：已经开发了用于制造用于MOSFET器件的直壁氮化硅封端的栅极结构的工艺。在直壁的氮化硅封盖的栅极结构的图案化期间，该工艺的特征在于产生用作蚀刻掩模的直壁光致抗蚀剂形状。具有约820至920埃之间的特定厚度范围的氮氧化硅层用作底部抗反射涂层（BARC），其位于上覆的直壁光致抗蚀剂形状和下面的氮化硅覆盖层之间。 BARC层在光刻曝光过程期间延迟从氮化硅覆盖层发射的反射，用于定义直壁光致抗蚀剂形状，允许获得所需的直壁光致抗蚀剂形状，而与其厚度无关氮化硅覆盖层。制造直壁，氮化硅封盖的栅极结构的能力允许控制和均匀化位于直壁，氮化硅封盖，栅极结构之下以及在源极/漏极区之间的沟道区域，与直线自对准围墙，氮化硅封盖，门结构。

17. 发明授权

US06916702B2 Gate process and gate structure for an embedded memory device 有权
标题翻译：嵌入式存储器件的栅极处理和栅极结构
公开(公告)号：US06916702B2
公开(公告)日：2005-07-12
申请号：US10951763
申请日：2004-09-29
申请人： Shih-Ming Chen , Hsiao-Ying Yang
发明人： Shih-Ming Chen , Hsiao-Ying Yang
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11531
摘要： A gate process and a gate process for an embedded memory device. A semiconductor silicon substrate has a memory cell area and a logic circuit area. A first dielectric layer is formed overlying the semiconductor silicon substrate, and then a gate structure is formed overlying the first dielectric layer of the memory cell area. Next, a protective layer is formed overlying the first dielectric layer and the top and sidewall of the gate structure. Next, an insulating spacer is formed overlying the protective layer disposed overlying the sidewall of the gate structure. Next, a pre-cleaning process is performed to remove the protective layer and the first dielectric layer overlying the logic circuit area. Next, a second dielectric layer is formed overlying the logic circuit area, and then a gate layer is formed overlying the second dielectric layer of the logic circuit area.
摘要翻译：嵌入式存储器件的栅极处理和栅极处理。半导体硅衬底具有存储单元区域和逻辑电路区域。在半导体硅衬底上形成第一电介质层，然后形成覆盖在存储单元区域的第一介电层上的栅极结构。接下来，形成覆盖第一电介质层和栅极结构的顶部和侧壁的保护层。接下来，形成覆盖在栅极结构的侧壁上的保护层的绝缘间隔物。接下来，执行预清洁处理以去除覆盖在逻辑电路区域上的保护层和第一介电层。接下来，形成覆盖逻辑电路区域的第二介电层，然后形成覆盖逻辑电路区域的第二介电层的栅极层。

18. 发明授权

US5819286A Video database indexing and query method and system 失效
标题翻译：视频数据库索引和查询方法和系统
公开(公告)号：US5819286A
公开(公告)日：1998-10-06
申请号：US570212
申请日：1995-12-11
申请人： Hsiao-Ying Yang , Cheng-Yao Ni , Chih-Hsing Yu , Chih-Chin Liu , Arbee L. P. Chen
发明人： Hsiao-Ying Yang , Cheng-Yao Ni , Chih-Hsing Yu , Chih-Chin Liu , Arbee L. P. Chen
IPC分类号： G06F17/30
CPC分类号： G06K9/00744 , G06F17/30831 , G06F17/30834 , G06K9/468 , Y10S707/99931 , Y10S707/99945
摘要： A video indexing and query execution system includes a processor which indexes video clips by: (a) identifying each symbol of one or more graphical icons in each frame of each video clip, (b) determining the horizontal, vertical and temporal coordinates of each symbol of the identified graphical icons, and (c) constructing a database for each identified symbol of the graphical icons. The processor converts a video query from graphical form to string form by: (a) receiving a video query specifying the vertical, horizontal and temporal coordinates of a graphical icon to be matched in at least one frame to be retrieved, and (b) constructing a normal 3-D string from the video query indicating the distance between each symbol of each icon in the video query in each direction. The processor also executes a video query on a video database by: (a) identifying only those video clips of the database whose signatures contain the signature of the executed video query, (b) for each of the identified video clips: (b1) constructing a 1-D list for each of the horizontal, vertical and temporal directions, comprising a plurality of sets of symbols of icons contained in video query, each set containing a permutation of symbols of the icons which satisfy the video query in the respective direction of the 1-D list, and (b2) forming the intersection of the three 1-D lists, and (c) identifying the portions of the video clips, indicated by a corresponding set contained in an intersection set of at least one of the identified video clips, as satisfying the video query.
摘要翻译：视频索引和查询执行系统包括：处理器，其通过以下步骤对视频剪辑进行索引：（a）识别每个视频剪辑的每个帧中的一个或多个图形图标的每个符号，（b）确定每个符号的水平，垂直和时间坐标的识别图形图标，以及（c）为图形图标的每个识别的符号构建数据库。处理器通过以下方式将视频查询转换成图形形式到字符串形式：（a）接收指定要在要检索的至少一个帧中匹配的图形图标的垂直，水平和时间坐标的视频查询，以及（b）构建来自视频查询的正常3-D字符串，指示每个方向上视频查询中每个图标的每个符号之间的距离。处理器还通过以下方式对视频数据库执行视频查询：（a）仅识别其签名包含执行的视频查询的签名的数据库的视频剪辑，（b）针对每个所识别的视频剪辑：（b1）构造用于水平，垂直和时间方向中的每一个的1-D列表，包括视频查询中包含的图标的多组符号集合，每个集合包含满足在相应方向上的视频查询的图标的符号排列所述1-D列表和（b2）形成三个1-D列表的交集，以及（c）识别由包含在所识别的至少一个的交集中的相应集合所指示的视频剪辑的部分视频剪辑，满足视频查询。

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