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11. 发明申请

US20050005068A1 Microprocessor with hot routine memory and method of operation 有权
标题翻译：微处理器带有常规内存和操作方法
公开(公告)号：US20050005068A1
公开(公告)日：2005-01-06
申请号：US10878514
申请日：2004-06-29
申请人： Hoi-Jin Lee
发明人： Hoi-Jin Lee
IPC分类号： G06F9/28 , G06F9/34 , G06F9/38 , G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/08 , G06F12/0842
摘要： Information designated as a hot routine by an application program is stored in a hot routine memory of the microprocessor system. A processor requests information, and a controller controls the hot routine memory to output information requested by a processor when the hot routine memory stores the requested information. The controller includes address translation information to translate the address used in the request from the processor to an address of the information in the hot routine memory.
摘要翻译：由应用程序指定为热程序的信息被存储在微处理器系统的热例程存储器中。处理器请求信息，并且当热例程存储器存储所请求的信息时，控制器控制热例程存储器以输出处理器请求的信息。控制器包括地址转换信息，以将来自处理器的请求中使用的地址转换为热例程存储器中的信息的地址。

12. 发明授权

US08949534B2 Multi-CPU system and computing system having the same 有权
标题翻译：多CPU系统和计算系统具有相同的功能
公开(公告)号：US08949534B2
公开(公告)日：2015-02-03
申请号：US13741717
申请日：2013-01-15
申请人： Hoi Jin Lee , Young Min Shin
发明人： Hoi Jin Lee , Young Min Shin
IPC分类号： G06F12/08 , G06F1/32
CPC分类号： G06F12/0811 , G06F1/3234 , G06F1/3275 , G06F12/0833 , G06F12/084 , G06F2212/1028 , G06F2212/283 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.
摘要翻译：一种多CPU数据处理系统，包括：多CPU处理器，包括：第一CPU，配置有至少第一内核，第一高速缓存和配置为访问第一高速缓存的第一高速缓存控制器; 以及配置有至少第二核心的第二CPU和被配置为访问第二高速缓存的第二高速缓存控制器，其中所述第一高速缓存由所述第二高速缓存的共享部分配置。

13. 发明授权

US08710891B2 Semiconductor IC including pulse generation logic circuit 有权
标题翻译：半导体IC包括脉冲生成逻辑电路
公开(公告)号：US08710891B2
公开(公告)日：2014-04-29
申请号：US13613501
申请日：2012-09-13
申请人： Hoi Jin Lee
发明人： Hoi Jin Lee
IPC分类号： H03K3/00
CPC分类号： H03K5/135
摘要： A pulse generation circuit includes storage elements disposed in a dispersed arrangement on a substrate and operating in response to a pulse signal, delay elements each proximate to a storage element receiving a clock signal and providing a delayed output signal, and a pulse generation logic circuit performing at least one logic operation on the clock signal and the plurality of delayed output signals to generate the pulse signal.
摘要翻译：脉冲发生电路包括以分散布置布置在衬底上并且响应于脉冲信号而工作的存储元件，每个接近存储元件的延迟元件接收时钟信号并提供延迟的输出信号，以及脉冲发生逻辑电路执行对时钟信号和多个延迟的输出信号进行至少一个逻辑运算以产生脉冲信号。

14. 发明授权

US08677166B2 Semiconductor devices and systems-on-chip having the same 有权
标题翻译：半导体器件和片上系统具有相同的功能
公开(公告)号：US08677166B2
公开(公告)日：2014-03-18
申请号：US13084924
申请日：2011-04-12
申请人： Heon-Hee Lee , Hoi-Jin Lee
发明人： Heon-Hee Lee , Hoi-Jin Lee
IPC分类号： G06F1/00 , H03L5/00
CPC分类号： H03K19/0013 , H03K19/00361 , H03K19/01721
摘要： A semiconductor device includes a power gating unit, a combinational logic unit and a clamping unit. The power gating unit is turned on to output an internal signal at an output electrode based on an input signal or turned off according to operation modes. The combinational logic unit includes an input electrode directly connected to the output electrode of the power gating unit through a data line, and generates an output signal based on the internal signal received through the data line. The clamping unit is turned on to clamp the internal signal at a logic high level or at a logic low level or turned off according to the operation modes. The semiconductor device clamps the output electrode of the power gating unit without degrading an operation speed of the semiconductor device.
摘要翻译：半导体器件包括电源门控单元，组合逻辑单元和夹紧单元。电源门控单元导通，根据输入信号在输出电极输出内部信号，或根据操作模式关闭。组合逻辑单元包括通过数据线直接连接到电力门控单元的输出电极的输入电极，并且基于通过数据线接收的内部信号产生输出信号。夹紧单元导通，根据操作模式将内部信号钳位在逻辑高电平或逻辑低电平或关闭。半导体器件夹紧功率选通单元的输出电极，而不会降低半导体器件的操作速度。

15. 发明申请

US20130241594A1 SCAN FLIP-FLOP CIRCUITS AND SCAN TEST CIRCUITS INCLUDING THE SAME 有权
标题翻译：扫描FLOP-FLOP电路和扫描测试电路，包括它们
公开(公告)号：US20130241594A1
公开(公告)日：2013-09-19
申请号：US13890517
申请日：2013-05-09
申请人： Hoi-Jin LEE , Bai-Sun KONG
发明人： Hoi-Jin LEE , Bai-Sun KONG
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K3/356182
摘要： A scan flip-flop circuit includes an input unit and an output unit. The data output unit is configured to provide a data output terminal with a data output signal in response to a data input signal and a first control signal in a first operation mode, and the data output unit is configured to prohibit the data output terminal from being provided with a power supply voltage and a ground voltage applied to the scan flip-flop circuit in response to the data input signal and the first control signal in a second operation mode. The scan output unit is configured to provide a scan output terminal with a scan output signal in response to a scan input signal and a second control signal in the second operation mode.
摘要翻译：扫描触发器电路包括输入单元和输出单元。数据输出单元被配置为在第一操作模式中响应于数据输入信号和第一控制信号向数据输出端提供数据输出信号，并且数据输出单元被配置为禁止数据输出端在第二操作模式中响应于数据输入信号和第一控制信号，提供施加到扫描触发器电路的电源电压和接地电压。扫描输出单元被配置为在第二操作模式中响应于扫描输入信号和第二控制信号向扫描输出端提供扫描输出信号。

16. 发明申请

US20110302540A1 SEMICONDUCTOR DEVICE COMPRISING SHIELD TREE AND RELATED LAYOUT METHOD 审中-公开
标题翻译：包含屏蔽树和相关布局方法的半导体器件
公开(公告)号：US20110302540A1
公开(公告)日：2011-12-08
申请号：US13041804
申请日：2011-03-07
申请人： Seok-Il KWON , Hoi Jin LEE
发明人： Seok-Il KWON , Hoi Jin LEE
IPC分类号： G06F17/50 , G01R31/26 , H05K9/00
CPC分类号： H01L23/5225 , G01R31/318572 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a plurality of flip-flops, a clock tree for transferring an externally input clock signal to the flip-flops, and a shield tree configured to shield the clock tree. The shield tree transmits a control signal to activate the flip-flops in a test operation mode of the semiconductor device.
摘要翻译：半导体器件包括多个触发器，用于将外部输入的时钟信号传送到触发器的时钟树，以及被配置为屏蔽时钟树的屏蔽树。屏蔽树在半导体器件的测试操作模式中发送控制信号以激活触发器。

17. 发明授权

US07539598B2 Semiconductor test apparatus and method thereof and multiplexer and method thereof 有权
标题翻译：半导体测试装置及其多路复用器及其方法
公开(公告)号：US07539598B2
公开(公告)日：2009-05-26
申请号：US10976038
申请日：2004-10-29
申请人： Mi-Sook Jang , Hoi-Jin Lee
发明人： Mi-Sook Jang , Hoi-Jin Lee
IPC分类号： G06F11/30 , G21C17/00 , G01R31/00 , G01R31/14
CPC分类号： G11C29/48 , G11C2029/3202
摘要： A semiconductor test apparatus for determining memory failure, including a first at least one multiplexer. The first at least one multiplexer may include a first transistor and a second transistor, the first transistor and the second transistor being different sizes. The semiconductor may include a scan cell, the scan cell including a second at least one multiplexer. The second at least one multiplexer may include a third transistor and a fourth transistor, the third transistor and the fourth transistor being different sizes. Another semiconductor test apparatus including a plurality of scan cells and a plurality of multiplexers, each of the plurality of scan cells and the plurality of multiplexers formed in a single wrapper.
摘要翻译：一种用于确定存储器故障的半导体测试装置，包括第一至少一个复用器。第一至少一个多路复用器可以包括第一晶体管和第二晶体管，第一晶体管和第二晶体管是不同的尺寸。半导体可以包括扫描单元，扫描单元包括第二至少一个复用器。第二至少一个多路复用器可以包括第三晶体管和第四晶体管，第三晶体管和第四晶体管是不同的尺寸。另一种半导体测试装置包括多个扫描单元和多个多路复用器，多个扫描单元和多个复用器中的每一个形成在单个封装中。

18. 发明申请

US20080209290A1 System-on-chip performing multi-phase scan chain and method thereof 有权
标题翻译：片上系统执行多相扫描链及其方法
公开(公告)号：US20080209290A1
公开(公告)日：2008-08-28
申请号：US12071106
申请日：2008-02-15
申请人： Hoi-Jin Lee
发明人： Hoi-Jin Lee
IPC分类号： G06F11/25
CPC分类号： G01R31/318544
摘要： A silicon on chip (SOC), may include function blocks, and a scan chain in each of the function blocks, the scan chains being adapted to conduct scan test operations in sync with a respective one of a plurality of clock signals having a different phase relative to each other, wherein during an isolation mode, the scan chains test combination circuits of the function blocks, and during an interface mode, the scan chains of adjacent ones of the function blocks test combination circuits between the adjacent ones of the function blocks.
摘要翻译：片上芯片（SOC）可以包括功能块和每个功能块中的扫描链，扫描链适于与具有不同相位的多个时钟信号中的相应一个进行扫描测试操作其中在隔离模式期间，扫描链测试功能块的组合电路，并且在接口模式期间，相邻功能块的扫描链测试相邻功能块之间的组合电路。

19. 发明授权

US07346737B2 Cache system having branch target address cache 有权
标题翻译：具有分支目标地址缓存的缓存系统
公开(公告)号：US07346737B2
公开(公告)日：2008-03-18
申请号：US11114464
申请日：2005-04-26
申请人： Hoi-Jin Lee
发明人： Hoi-Jin Lee
IPC分类号： G06F12/00
CPC分类号： G06F9/3804 , G06F12/0875 , Y02D10/13
摘要： A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The BTAC access bits represent a presence of a branch instruction on the next cache line of a cache line corresponding to the instruction cache. The BTAC is selectively accessed in accordance with values of the BTAC access bits corresponding to I'th (I is a positive integer) cache lines presently accessed in the instruction cache.
摘要翻译：缓存系统具有分支目标地址高速缓存，包括存储单元，用于存储分别对应于指令高速缓存行的高速缓存行的目标地址高速缓存（BTAC）访问位。 BTAC访问位表示在对应于指令高速缓存的高速缓存行的下一个高速缓存行上存在分支指令。根据当前在指令高速缓存中访问的I'th（I是正整数）高速缓存行的BTAC访问位的值有选择地访问BTAC。

20. 发明授权

US07260754B2 Semiconductor device with speed binning test circuit and test method thereof 有权
标题翻译：具有速度分组测试电路的半导体器件及其测试方法
公开(公告)号：US07260754B2
公开(公告)日：2007-08-21
申请号：US10720123
申请日：2003-11-25
申请人： Hoi-Jin Lee
发明人： Hoi-Jin Lee
IPC分类号： G01R31/28
CPC分类号： G11C29/025 , G01R31/31718 , G01R31/31725 , G11C29/02 , G11C29/50012
摘要： A speed binning test circuit for a semiconductor device may include a plurality of circuit groups arranged along a boundary of a chip circuit. Each circuit group may include a different number of unit delay circuits that may form a chain structure. The speed binning test circuit may also include a plurality of pads. Each pad may be arranged between a pair of circuit groups so that at least one output terminal of a unit delay circuit of one of the plurality of circuit groups is connected to one of the pads. The speed binning test device performs a speed binning test method in which a signal through the circuit groups is delayed, and on-chip-variations are monitored to determine a total signal delay time through the chain structure.
摘要翻译：用于半导体器件的速度合并测试电路可以包括沿着芯片电路的边界布置的多个电路组。每个电路组可以包括可以形成链结构的不同数量的单位延迟电路。速度合并测试电路还可以包括多个焊盘。每个焊盘可以布置在一对电路组之间，使得多个电路组之一的单元延迟电路的至少一个输出端子连接到其中一个焊盘。速度分档测试装置执行速度合并测试方法，其中通过电路组的信号被延迟，并且监视片上变化以确定通过链结构的总信号延迟时间。

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