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1. 发明授权

US09158354B2 Footer-less NP domino logic circuit and related apparatus 有权
标题翻译：无脚踏NP多米诺逻辑电路及相关设备
公开(公告)号：US09158354B2
公开(公告)日：2015-10-13
申请号：US13795852
申请日：2013-03-12
申请人： Ken Keon Shin , Hoi Jin Lee , Gun Ok Jung , Min Su Kim
发明人： Ken Keon Shin , Hoi Jin Lee , Gun Ok Jung , Min Su Kim
IPC分类号： G06F1/04 , G06F1/32 , H03K19/00 , H03K19/096
CPC分类号： G06F1/32 , G06F1/04 , H03K19/0008 , H03K19/0963
摘要： A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node.
摘要翻译：多米诺骨牌逻辑电路包括响应于时钟信号对第一动态节点预充电的预充电电路，第一逻辑网络响应于第一数据信号确定第一动态节点的逻辑电平，反相器接收时钟信号响应于逆变器的输出信号而放电第二动态节点的放电电路，以及响应于至少一个第二数据信号和第一动态节点的输出信号确定第二动态节点的逻辑电平的第二逻辑网络节点。

2. 发明授权

US08779828B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08779828B2
公开(公告)日：2014-07-15
申请号：US13417531
申请日：2012-03-12
申请人： Heon-hee Lee , Hoi-jin Lee , Taek-kyun Shin
发明人： Heon-hee Lee , Hoi-jin Lee , Taek-kyun Shin
IPC分类号： H03L5/00
CPC分类号： H03K19/017509
摘要： A semiconductor device including a first function block operating at a first operation voltage having a first range and for generating a data signal, a second function block operating at a second operation voltage having a second range, and a voltage level control unit for performing or not performing a level shifting operation on a voltage level of the data signal depending on the existence or non-existence of a difference between the first operation voltage and the second operation voltage, and for transmitting a level-shifted data signal or the data signal to the second function block.
摘要翻译：一种半导体器件，包括在具有第一范围的第一操作电压下工作并用于产生数据信号的第一功能块，在具有第二范围的第二操作电压下操作的第二功能块，以及用于执行或不执行的电压电平控制单元根据第一操作电压和第二操作电压之间的差的存在或不存在，对数据信号的电压电平执行电平移位操作，并且将电平移位数据信号或数据信号发送到第二功能块。

3. 发明申请

US20130214840A1 SEMICONDUCTOR IC INCLUDING PULSE GENERATION LOGIC CIRCUIT 有权
标题翻译：包括脉冲发生逻辑电路的半导体IC
公开(公告)号：US20130214840A1
公开(公告)日：2013-08-22
申请号：US13613501
申请日：2012-09-13
申请人： HOI JIN LEE
发明人： HOI JIN LEE
IPC分类号： H03H11/26
CPC分类号： H03K5/135
摘要： A pulse generation circuit includes storage elements disposed in a dispersed arrangement on a substrate and operating in response to a pulse signal, delay elements each proximate to a storage element receiving a clock signal and providing a delayed output signal, and a pulse generation logic circuit performing at least one logic operation on the clock signal and the plurality of delayed output signals to generate the pulse signal.
摘要翻译：脉冲发生电路包括以分散布置布置在衬底上并且响应于脉冲信号而工作的存储元件，每个接近存储元件的延迟元件接收时钟信号并提供延迟的输出信号，以及脉冲发生逻辑电路执行对时钟信号和多个延迟的输出信号进行至少一个逻辑运算以产生脉冲信号。

4. 发明申请

US20130194019A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATING DEVICE INCLUDING THE SAME 审中-公开
标题翻译：半导体集成电路及其操作装置的方法
公开(公告)号：US20130194019A1
公开(公告)日：2013-08-01
申请号：US13613953
申请日：2012-09-13
申请人： Hoi Jin Lee , Gun Ok Jung
发明人： Hoi Jin Lee , Gun Ok Jung
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , H03K3/356156
摘要： The semiconductor integrated circuit includes a clock tree that transmits a clock signal to a plurality of tree branches, a plurality of pulse generators, and a plurality of pulse distribution networks. Each pulse generator generates a pulse in response to the clock signal transmitted through the tree branches. Each pulse distribution network is in communication with a pulse generator of the plurality of pulse generators, and is constructed and arranged to transmit the pulse generated by each pulse generator to a plurality of pulse sinks.
摘要翻译：半导体集成电路包括将时钟信号发送到多个树枝，多个脉冲发生器和多个脉冲分配网络的时钟树。每个脉冲发生器响应于通过树枝传输的时钟信号产生脉冲。每个脉冲分配网络与多个脉冲发生器中的脉冲发生器通信，并且被构造和布置成将由每个脉冲发生器产生的脉冲发送到多个脉冲发生器。

5. 发明授权

US07893718B2 High-speed multiplexer and semiconductor device including the same 有权
标题翻译：高速多路复用器和包括相同的半导体器件
公开(公告)号：US07893718B2
公开(公告)日：2011-02-22
申请号：US12540465
申请日：2009-08-13
申请人： Sung Bae Park , Gun Ok Jung , Young Min Shin , Hoi Jin Lee , Chang Jun Choi , Min Su Kim
发明人： Sung Bae Park , Gun Ok Jung , Young Min Shin , Hoi Jin Lee , Chang Jun Choi , Min Su Kim
IPC分类号： H03K19/094
CPC分类号： H03K19/1737 , H03K17/005 , H03K17/693 , H03K19/0013 , H03K2217/0036
摘要： High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.
摘要翻译：高速多路复用器包括第一N-1选择电路，其中N是大于1的整数，第二N-1选择电路和输出驱动器。第一N-1选择电路被配置为响应于第一多位选择信号将所选择的第一输入信号（从N个输入信号中）的真或互补版本路由到其输出，其中N是大于1的整数。第二N-1选择电路被配置为响应于第二多位选择信号将所选择的第一输入信号的真实或互补版本路由到其输出。输出驱动器包括上拉电路，其响应于在第一N-1选择电路的输出处产生的信号，以及下拉电路，其响应于在输出端产生的信号第二个N到1选择电路。

6. 发明授权

US07631146B2 Processor with cache way prediction and method thereof 有权
标题翻译：具有缓存方式预测的处理器及其方法
公开(公告)号：US07631146B2
公开(公告)日：2009-12-08
申请号：US11264158
申请日：2005-11-02
申请人： Gi-ho Park , Hoi-jin Lee
发明人： Gi-ho Park , Hoi-jin Lee
IPC分类号： G06F12/00
CPC分类号： G06F9/3844 , G06F9/3806 , G06F9/3814 , G06F12/0864 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： A processor with cache way prediction and method thereof. The processor includes a cache way prediction unit for predicting at least one cache way for selection from a plurality of cache ways. The processor may further include an instruction cache for accessing the selected at least one cache way, where the selected at least one cache way is less than all of the plurality of cache ways. The method includes predicting less than all of a plurality of cache ways for selection and accessing the selected less than all of the plurality of cache ways. In both the process and method thereof, by accessing less than all of the plurality of cache ways, a power consumption and delay may be reduced.
摘要翻译：一种具有缓存方式预测的处理器及其方法。处理器包括一个缓存方式预测单元，用于从多个高速缓存路径预测至少一个用于选择的高速缓存路径。处理器还可以包括用于访问所选择的至少一个高速缓存方式的指令高速缓存，其中所选择的至少一个高速缓存方式小于所述多个高速缓存路径中的所有高速缓存路径。该方法包括预测小于所有多个高速缓存路径以选择和访问所选择的少于所有多个高速缓存路径。在其处理和方法中，通过访问少于所有多个高速缓存路径，可以减少功耗和延迟。

7. 发明申请

US20050268040A1 Cache system having branch target address cache 有权
标题翻译：具有分支目标地址缓存的缓存系统
公开(公告)号：US20050268040A1
公开(公告)日：2005-12-01
申请号：US11114464
申请日：2005-04-26
申请人： Hoi-Jin Lee
发明人： Hoi-Jin Lee
IPC分类号： G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F9/3804 , G06F12/0875 , Y02D10/13
摘要： A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The BTAC access bits represent a presence of a branch instruction on the next cache line of a cache line corresponding to the instruction cache. The BTAC is selectively accessed in accordance with values of the BTAC access bits corresponding to I'th (I is a positive integer) cache lines presently accessed in the instruction cache.
摘要翻译：缓存系统具有分支目标地址高速缓存，包括存储单元，用于存储分别对应于指令高速缓存行的高速缓存行的目标地址高速缓存（BTAC）访问位。 BTAC访问位表示在对应于指令高速缓存的高速缓存行的下一个高速缓存行上存在分支指令。根据当前在指令高速缓存中访问的I'th（I是正整数）高速缓存行的BTAC访问位的值有选择地访问BTAC。

8. 发明授权

US06931462B2 Memory controller which increases bus bandwidth, data transmission method using the same, and computer system having the same 有权
标题翻译：增加总线带宽的存储器控制器，使用其的数据传输方法，以及具有相同的计算机系统
公开(公告)号：US06931462B2
公开(公告)日：2005-08-16
申请号：US10619037
申请日：2003-07-14
申请人： Hoi-jin Lee
发明人： Hoi-jin Lee
IPC分类号： G06F12/06 , G06F3/00 , G06F12/00 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/40 , G11C8/00
CPC分类号： G06F13/1684 , G06F13/4018
摘要： A memory controller increases the effective bus bandwidth of a computer system. The memory controller includes a first port and a second port which receive and transmit N-bit data values, respectively; a third port receiving and transmitting 2N-bit data values; and a fourth port and a fifth port receiving and transmitting the N-bit data values, respectively. Here, two N-bit data values are simultaneously fetched from a memory device corresponding to the first port via the first port and a memory device corresponding to the second port in response to a command signal and an address input via the third port, the two fetched N-bit data values are combined into a 2N-bit data value, and the 2N-bit data value is transmitted to the third port. In addition, an N-bit data value is fetched from a corresponding memory device via the first port and/or second port in response to a command signal and address input via the fourth port and/or fifth port, and the fetched N-bit data value is transmitted to the fourth port and/or fifth port.
摘要翻译：存储器控制器增加计算机系统的有效总线带宽。存储器控制器包括分别接收和发送N位数据值的第一端口和第二端口; 第三端口接收和发送2N位数据值; 以及分别接收和发送N位数据值的第四端口和第五端口。这里，响应于通过第三端口输入的命令信号和地址，经由第一端口和对应于第二端口的存储器件从与第一端口对应的存储器件中同时取出两个N位数据值，读取的N位数据值被组合成2N位数据值，并且2N位数据值被发送到第三端口。此外，响应于经由第四端口和/或第五端口输入的命令信号和地址，经由第一端口和/或第二端口从对应的存储器件取出N位数据值，并且获取的N位数据值被发送到第四端口和/或第五端口。

9. 发明申请

US20050091561A1 Scan test method, device, and system 审中-公开
标题翻译：扫描测试方法，设备和系统
公开(公告)号：US20050091561A1
公开(公告)日：2005-04-28
申请号：US10947209
申请日：2004-09-23
申请人： Hoi-Jin Lee
发明人： Hoi-Jin Lee
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G11C29/00 , G11C29/48 , H01L21/822 , H01L27/04 , H03K19/00
CPC分类号： G01R31/318536 , G11C29/48 , G11C2029/0401 , G11C2029/3202
摘要： A scan test method, device, and system may be provided to detect faults in embedded memories. The device may include a first select unit which may selectively output data inputs and may detect the faults in the embedded memories in response to a select signal S, a second select unit which may selectively output a data input from the first select unit and/or a scan input from an input terminal in response to a scan enable signal SE, and a flip-flop which may output data output from the second select unit to an output terminal in response to a clock signal CK.
摘要翻译：可以提供扫描测试方法，设备和系统来检测嵌入式存储器中的故障。设备可以包括第一选择单元，其可以选择性地输出数据输入并且可以响应于选择信号S来检测嵌入式存储器中的故障;第二选择单元，其可以选择性地输出来自第一选择单元的数据输入和/或响应于扫描使能信号SE从输入端子的扫描输入，以及触发器，其可以响应于时钟信号CK将从第二选择单元输出的数据输出到输出端子。

10. 发明申请

US20050028116A1 Method of HDL simulation considering hard macro core with negative setup/hold time 有权
标题翻译：考虑具有负设置/保持时间的硬宏核心的HDL仿真方法
公开(公告)号：US20050028116A1
公开(公告)日：2005-02-03
申请号：US10867726
申请日：2004-06-16
申请人： Mi-Sook Jang , Hoi-Jin Lee
发明人： Mi-Sook Jang , Hoi-Jin Lee
IPC分类号： G06F9/45 , G06F17/50 , G06G7/62 , H01L21/82
CPC分类号： G06F17/5022
摘要： A method of HDL simulation is described, which may enhance HDL simulation accuracy by allowing a simulator to process a negative setup time and/or hold time. For an electronic circuit device negative setup time and/or a negative hold time, a simulation may be executed without altering the negative setup time and/or hold time to be interpreted as zero. A setup time and/or hold time may be negative relative to a particular clock cycle while being positive relative to another clock cycle. Incorporating the value of the negative setup time and/or hold time without altering its value to zero may increase the accuracy of HDL simulations.
摘要翻译：描述了HDL仿真的方法，其可以通过允许模拟器处理负建立时间和/或保持时间来提高HDL仿真精度。对于电子电路装置负建立时间和/或负保持时间，可以执行模拟而不改变负建立时间和/或保持时间以被解释为零。相对于特定的时钟周期，建立时间和/或保持时间可以是负的，而相对于另一个时钟周期是正的。结合负建立时间和/或保持时间的值而不将其值改变为零可能会提高HDL仿真的准确性。

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